twiddling gpio successfully

1 files changed, 71 insertions, 64 deletions

diff --git a/usrp/host/lib/db_wbxng_adf4350_regs.cc b/usrp/host/lib/db_wbxng_adf4350_regs.cc
index b320e8bbf..3452663c8 100644
--- a/usrp/host/lib/db_wbxng_adf4350_regs.cc
+++ b/usrp/host/lib/db_wbxng_adf4350_regs.cc
@@ -6,47 +6,54 @@
 #include <usrp/db_wbxng_adf4350.h>
 //#include "cal_div.h"
 
+/* reg 0 */
+/* reg 1 */
+const uint8_t adf4350_regs::s_prescaler = 1;
+const uint16_t adf4350_regs::s_phase = 0;
+/* reg 2 */
+const uint8_t adf4350_regs::s_low_noise_and_low_spur_modes = 0;
+const uint8_t adf4350_regs::s_muxout = 6;
+const uint8_t adf4350_regs::s_reference_doubler = 1;
+const uint8_t adf4350_regs::s_rdiv2 = 0;
+const uint8_t adf4350_regs::s_double_buff = 0;
+const uint8_t adf4350_regs::s_charge_pump_setting = 7;
+const uint8_t adf4350_regs::s_ldf = 0;
+const uint8_t adf4350_regs::s_ldp = 0;
+const uint8_t adf4350_regs::s_pd_polarity = 1;
+const uint8_t adf4350_regs::s_power_down = 0;
+const uint8_t adf4350_regs::s_cp_three_state = 0;
+const uint8_t adf4350_regs::s_counter_reset = 0;
+/* reg 3 */
+const uint8_t adf4350_regs::s_csr = 0;
+const uint8_t adf4350_regs::s_clk_div_mode = 0;
+const uint16_t adf4350_regs::s_12_bit_clock_divider_value = 0;
+/* reg 4 */
+const uint8_t adf4350_regs::s_feedback_select = 1;
+const uint8_t adf4350_regs::s_vco_power_down = 0;
+const uint8_t adf4350_regs::s_mtld = 0;
+const uint8_t adf4350_regs::s_aux_output_select = 0;
+const uint8_t adf4350_regs::s_aux_output_enable = 0;
+const uint8_t adf4350_regs::s_aux_output_power = 0;
+const uint8_t adf4350_regs::s_rf_output_enable = 1;
+const uint8_t adf4350_regs::s_output_power = 1;
+/* reg 5 */
+const uint8_t adf4350_regs::s_ld_pin_mode = 1;
+
 adf4350_regs::adf4350_regs(adf4350* _adf4350){
     d_adf4350 = _adf4350;
 
     /* reg 0 */
-    _int = uint16_t(100);
-    _frac = 0;
+    d_int = uint16_t(100);
+    d_frac = 0;
     /* reg 1 */
-    _prescaler = 1;                        /* 8/9 */
-    _phase = 0;                           /* 0 */
-    _mod = uint16_t(0xfff);                      /* max fractional accuracy */
+    d_mod = uint16_t(0xfff);                      /* max fractional accuracy */
     /* reg 2 */
-    _low_noise_and_low_spur_modes = 0;     /* low noise mode */
-    _muxout = 6;                           /* digital lock detect */
-    _reference_doubler = 1;                /* enabled */
-    _rdiv2 = 0;                            /* disabled */
-    _10_bit_r_counter = uint16_t(1);
-    _double_buff = 0;                      /* disabled */
-    _charge_pump_setting = 7;              /* 2.50 mA */
-    _ldf = 0;                              /* frac-n */
-    _ldp = 0;                              /* 10 ns */
-    _pd_polarity = 1;                      /* positive */
-    _power_down = 0;                       /* disabled */
-    _cp_three_state = 0;                   /* disabled */
-    _counter_reset = 0;                    /* disabled */
+    d_10_bit_r_counter = uint16_t(1);
     /* reg 3 */
-    _csr = 0;                              /* disabled */
-    _clk_div_mode = 0;                     /* clock divider off */
-    _12_bit_clock_divider_value = 0;      /* 0 */
     /* reg 4 */
-    _feedback_select = 1;                  /* fundamental */
-    _divider_select = 0;
-    _8_bit_band_select_clock_divider_value = 0;
-    _vco_power_down = 0;                   /* vco powered up */
-    _mtld = 0;                             /* mute disabled */
-    _aux_output_select = 0;                /* divided output */
-    _aux_output_enable = 0;                /* disabled */
-    _aux_output_power = 0;                 /* -4 */
-    _rf_output_enable = 1;                 /* enabled */
-    _output_power = 1;                     /* -1 */
+    d_divider_select = 0;
+    d_8_bit_band_select_clock_divider_value = 0;
     /* reg 5 */
-    _ld_pin_mode = 1;                      /* digital lock detect */
 }
 
 adf4350_regs::~adf4350_regs(void){
@@ -62,43 +69,43 @@ adf4350_regs::_load_register(uint8_t addr){
 	uint32_t data;
 	switch (addr){
 		case 0: data = (
-			_reg_shift(_int, 15)                           |
-			_reg_shift(_frac, 3)); break;
+			_reg_shift(d_int, 15)                           |
+			_reg_shift(d_frac, 3)); break;
 		case 1: data = (
-			_reg_shift(_prescaler, 27)                     |
-			_reg_shift(_phase, 15)                         |
-			_reg_shift(_mod, 3)); break;
+			_reg_shift(s_prescaler, 27)                     |
+			_reg_shift(s_phase, 15)                         |
+			_reg_shift(d_mod, 3)); break;
 		case 2: data = (
-			_reg_shift(_low_noise_and_low_spur_modes, 29)  |
-			_reg_shift(_muxout, 26)                        |
-			_reg_shift(_reference_doubler, 25)             |
-			_reg_shift(_rdiv2, 24)                         |
-			_reg_shift(_10_bit_r_counter, 14)              |
-			_reg_shift(_double_buff, 13)                   |
-			_reg_shift(_charge_pump_setting, 9)            |
-			_reg_shift(_ldf, 8)                            |
-			_reg_shift(_ldp, 7)                            |
-			_reg_shift(_pd_polarity, 6)                    |
-			_reg_shift(_power_down, 5)                     |
-			_reg_shift(_cp_three_state, 4)                 |
-			_reg_shift(_counter_reset, 3)); break;
+			_reg_shift(s_low_noise_and_low_spur_modes, 29)  |
+			_reg_shift(s_muxout, 26)                        |
+			_reg_shift(s_reference_doubler, 25)             |
+			_reg_shift(s_rdiv2, 24)                         |
+			_reg_shift(d_10_bit_r_counter, 14)              |
+			_reg_shift(s_double_buff, 13)                   |
+			_reg_shift(s_charge_pump_setting, 9)            |
+			_reg_shift(s_ldf, 8)                            |
+			_reg_shift(s_ldp, 7)                            |
+			_reg_shift(s_pd_polarity, 6)                    |
+			_reg_shift(s_power_down, 5)                     |
+			_reg_shift(s_cp_three_state, 4)                 |
+			_reg_shift(s_counter_reset, 3)); break;
 		case 3: data = (
-			_reg_shift(_csr, 18)                           |
-			_reg_shift(_clk_div_mode, 15)                  |
-			_reg_shift(_12_bit_clock_divider_value, 3)); break;
+			_reg_shift(s_csr, 18)                           |
+			_reg_shift(s_clk_div_mode, 15)                  |
+			_reg_shift(s_12_bit_clock_divider_value, 3)); break;
 		case 4: data = (
-			_reg_shift(_feedback_select, 23)               |
-			_reg_shift(_divider_select, 20)                |
-			_reg_shift(_8_bit_band_select_clock_divider_value, 12) |
-			_reg_shift(_vco_power_down, 11)                |
-			_reg_shift(_mtld, 10)                          |
-			_reg_shift(_aux_output_select, 9)              |
-			_reg_shift(_aux_output_enable, 8)              |
-			_reg_shift(_aux_output_power, 6)               |
-			_reg_shift(_rf_output_enable, 5)               |
-			_reg_shift(_output_power, 3)); break;
+			_reg_shift(s_feedback_select, 23)               |
+			_reg_shift(d_divider_select, 20)                |
+			_reg_shift(d_8_bit_band_select_clock_divider_value, 12) |
+			_reg_shift(s_vco_power_down, 11)                |
+			_reg_shift(s_mtld, 10)                          |
+			_reg_shift(s_aux_output_select, 9)              |
+			_reg_shift(s_aux_output_enable, 8)              |
+			_reg_shift(s_aux_output_power, 6)               |
+			_reg_shift(s_rf_output_enable, 5)               |
+			_reg_shift(s_output_power, 3)); break;
 		case 5: data = (
-			_reg_shift(_ld_pin_mode, 22)); break;
+			_reg_shift(s_ld_pin_mode, 22)); break;
 		default: return;
 	}
 	/* write the data out to spi */