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author | Josh Blum | 2010-03-16 18:22:10 -0700 |
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committer | Josh Blum | 2010-03-16 18:22:10 -0700 |
commit | d43d40813c1a8343a86abb231876a8b7c0e9f806 (patch) | |
tree | e919c7da99aca7918ca5533e899cd7c9bbbf76bd /usrp/fpga/megacells/fifo_1kx16.cmp | |
parent | 19d3c0cab37123f8bfd19fdfc576f44b6069300f (diff) | |
parent | ac422b700282e21956dbf7643ee2dfbeeebdaf45 (diff) | |
download | gnuradio-d43d40813c1a8343a86abb231876a8b7c0e9f806.tar.gz gnuradio-d43d40813c1a8343a86abb231876a8b7c0e9f806.tar.bz2 gnuradio-d43d40813c1a8343a86abb231876a8b7c0e9f806.zip |
Merge branch 'master' of http://gnuradio.org/git/gnuradio into uhd
Diffstat (limited to 'usrp/fpga/megacells/fifo_1kx16.cmp')
-rwxr-xr-x | usrp/fpga/megacells/fifo_1kx16.cmp | 30 |
1 files changed, 0 insertions, 30 deletions
diff --git a/usrp/fpga/megacells/fifo_1kx16.cmp b/usrp/fpga/megacells/fifo_1kx16.cmp deleted file mode 100755 index 9b2c2c0c3..000000000 --- a/usrp/fpga/megacells/fifo_1kx16.cmp +++ /dev/null @@ -1,30 +0,0 @@ ---Copyright (C) 1991-2006 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions
---and other software and tools, and its AMPP partner logic
---functions, and any output files any of the foregoing
---(including device programming or simulation files), and any
---associated documentation or information are expressly subject
---to the terms and conditions of the Altera Program License
---Subscription Agreement, Altera MegaCore Function License
---Agreement, or other applicable license agreement, including,
---without limitation, that your use is for the sole purpose of
---programming logic devices manufactured by Altera and sold by
---Altera or its authorized distributors. Please refer to the
---applicable agreement for further details.
-
-
-component fifo_1kx16
- PORT
- (
- aclr : IN STD_LOGIC ;
- clock : IN STD_LOGIC ;
- data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
- rdreq : IN STD_LOGIC ;
- wrreq : IN STD_LOGIC ;
- almost_empty : OUT STD_LOGIC ;
- empty : OUT STD_LOGIC ;
- full : OUT STD_LOGIC ;
- q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
- usedw : OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
- );
-end component;
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