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-- All rights reserved. 

-- This file is part of VESTs (Vhdl tESTs).

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-- ---------------------------------------------------------------------
--
-- $Id: test183.ams,v 1.1 2002-03-27 22:11:20 paw Exp $
-- $Revision: 1.1 $
--
-- ---------------------------------------------------------------------

-- this model tests for the correst implementation of the 'above 
-- statement.
PACKAGE electricalSystem IS
    NATURE electrical IS real ACROSS real THROUGH;
    FUNCTION SIN(X : real) RETURN real;
    alias ground is electrical'reference;
END PACKAGE electricalSystem;

use work.electricalsystem.all;

entity product is 
generic(bound:real:=1.0);
port(
     quantity out1:real);
end product;

architecture pro of product is
constant in1:real:=10.0;
constant in2:real:=1.0;
signal outofbound:out boolean;

begin
	outofbound<=true;
	out1== in1*in2;
	outofbound<=out1'above(bound);

end pro;