-- Copyright (C) 2001-2002 The University of Cincinnati.  
-- All rights reserved. 

-- This file is part of VESTs (Vhdl tESTs).

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-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
-- June 1991. A copy of this license agreement can be found in the file
-- "COPYING", distributed with this archive.

-- You should have received a copy of the GNU General Public License
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-- ---------------------------------------------------------------------
--
-- $Id: test175.ams,v 1.1 2002-03-27 22:11:20 paw Exp $
-- $Revision: 1.1 $
--
-- ---------------------------------------------------------------------

----------------------------------------------------------------------
-- SIERRA REGRESSION TESTING MODEL
-- Develooped at:
-- Distriburted Processing Laboratory
-- University of Cincinnati
----------------------------------------------------------------------
-- File          : test175.ams
-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
-- Created       : Sept 2001
----------------------------------------------------------------------
-- Description :
----------------------------------------------------------------------
-- the test is done for checking the correct implementation
-- of the simultaneous case statement.it checks
-- nature declaration, terminal and quantity declarations

PACKAGE electricalSystem IS
    NATURE electrical IS real ACROSS real THROUGH Ground reference ;
    FUNCTION  SIN (X : real ) RETURN real;
    FUNCTION  EXP  (X : real ) RETURN real;
END PACKAGE electricalSystem;


USE work.electricalSystem.all;

ENTITY simcase IS
END simcase;

ARCHITECTURE asimcase OF simcase IS

    terminal T1, T2 : electrical;

    quantity v1 across i1 through T1 ;
    quantity v2 across i2 through T1 to T2;
    quantity v3 across i3 through T2 ;

BEGIN  

      eqn1 : v1 == 1.0;
      eqn2 : v2 == 2.0;	     
c1:	case (v1*2.0) use
       
            when (2.0) use 
                       if (v2==2.0) use
			v2 == i2 * 100.0;
		       else
			v2 ==i2*10.0;
            	       end use;
	    when (6.0) use
                       v2 == i2 * 200.0;
            when (10.0) use
                       v2 == i2 * 300.0;
	end case c1;
END asimcase ;