-- Copyright (C) 2001-2002 The University of Cincinnati.  
-- All rights reserved. 

-- This file is part of VESTs (Vhdl tESTs).

-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
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-- You may modify, distribute, and use the software contained in this
-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
-- June 1991. A copy of this license agreement can be found in the file
-- "COPYING", distributed with this archive.

-- You should have received a copy of the GNU General Public License
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 

-- ---------------------------------------------------------------------
--
-- $Id: test173.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
-- $Revision: 1.1 $
--
-- ---------------------------------------------------------------------

----------------------------------------------------------------------
-- SIERRA REGRESSION TESTING MODEL
-- Develooped at:
-- Distriburted Processing Laboratory
-- University of Cincinnati
----------------------------------------------------------------------
-- File          : test173.ams
-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
-- Created       : Sept 2001
----------------------------------------------------------------------
-- Description :
----------------------------------------------------------------------
-- the test is done for checking the correct implementation
-- of the simultaneous if equation statement.it checks
-- nature declaration, terminal and quantity declarations.

PACKAGE electricalSystem IS
    NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE;
    FUNCTION SIN(X : real) RETURN real;
    FUNCTION EXP(X : real) RETURN real;
END PACKAGE electricalSystem;
use work.electricalSystem.all;

entity test is
end entity;

architecture atest of test is
terminal t1, t2: electrical;
quantity v1 across i1 through t1 to t2;
quantity v2 across t2;

begin
e1: v1== 1.0;
e2: v2==0.0;

	if (v1==1.0) use
	  output <= '1';
	end use;

	if (v2==2.0) use
	   output <='1';
	end use;
end architecture atest;