-- Copyright (C) 2001-2002 The University of Cincinnati.  
-- All rights reserved. 

-- This file is part of VESTs (Vhdl tESTs).

-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
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-- intellectual property laws, and all other applicable laws of the U.S.,
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-- You may modify, distribute, and use the software contained in this
-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
-- June 1991. A copy of this license agreement can be found in the file
-- "COPYING", distributed with this archive.

-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 

-- ---------------------------------------------------------------------
--
-- $Id: test164.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
-- $Revision: 1.1 $
--
-- ---------------------------------------------------------------------

----------------------------------------------------------------------
-- SIERRA REGRESSION TESTING MODEL
-- Develooped at:
-- Distriburted Processing Laboratory
-- University of Cincinnati
-- Cincinnati
----------------------------------------------------------------------
-- File          : test164.ams
-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
-- Created       : Sept 2001
----------------------------------------------------------------------
-- Description :
----------------------------------------------------------------------
-- A simple rc model...with 2 res in parallel connected thru a capacitor
-- -------------||-----
--           |        |
--           | R      | R
-- --------------------		
-- the test is done for checking the correct implementation of the simple
-- simultaneous equation statement.it checks nature declaration, terminal,
-- 'dot, 'integ and quantity declarations. 

PACKAGE electricalSystem IS
    NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE;
    FUNCTION SIN(X : real) RETURN real;
    FUNCTION EXP(X : real) RETURN real;
END PACKAGE electricalSystem;
use work.electricalSystem.all;

entity test is
end entity;

architecture atest of test is
terminal T1,T2:electrical;
quantity VR1 across IR1 through T1;
quantity VC across IC through T1 to T2;
quantity VR2 across IR2 through T2;
quantity VS across T1;

begin

e1:     VR1 == IR1*100.0;
e2:     IC  == VC'dot *1.0e-12;
e3:     VR2 == IR2*10.0;
e4:     VC == IC'integ/1.0e15
esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12);

end architecture atest;