-- Copyright (C) 2001-2002 The University of Cincinnati.  
-- All rights reserved. 

-- This file is part of VESTs (Vhdl tESTs).

-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
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-- You may modify, distribute, and use the software contained in this
-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
-- June 1991. A copy of this license agreement can be found in the file
-- "COPYING", distributed with this archive.

-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 

-- ---------------------------------------------------------------------
--
-- $Id: test179.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
-- $Revision: 1.1 $
--
-- ---------------------------------------------------------------------

----------------------------------------------------------------------
-- SIERRA REGRESSION TESTING MODEL
-- Develooped at:
-- Distriburted Processing Laboratory
-- University of Cincinnati
-- Cincinnati
----------------------------------------------------------------------
-- File          : test179.ams
-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
-- Created       : Sept 2001
----------------------------------------------------------------------
-- Description :
----------------------------------------------------------------------
-- A simple resistor model...
-- the test is done for checking the correct implementation
-- 'instance_name attribute

PACKAGE electricalSystem IS
    NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE;
    FUNCTION  SIN (X : real ) RETURN real;
    FUNCTION  EXP  (X : real ) RETURN real;
END PACKAGE electricalSystem;


USE work.electricalSystem.all;

ENTITY Bottom IS
generic(GBottom:integer);
port (PBottom:integer);
constant SBottom:integer:=4;
END Bottom;

ARCHITECTURE BottomArch OF Bottom IS
begin
--	SBottom :=4;
	ProcessBottom: process
		variable V:integer;
	begin
		if GBottom=4 then
		 assert 
		 V'Instance_Name=":top(top):b1:b2:g1(4):b3:11@bottom(bottomarch):processbottom:v"
		 and 
		 GBottom'Instance_Name=":top(top):b1:b2:g1(4):b3:11@bottom(bottomarch):gbottom";
		elsif GBottom=1 then
		   assert 
                   V'Instance_Name=":top(top):12@bottom(bottomarch):processbottom:v";
		else
		   assert
		   GBottom'Instance_Name= ":top(top):12@bottom(bottomarch):gbottom";
		end if;
		wait;
	end process ProcessBottom;
end architecture BottomArch;