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-- All rights reserved. 

-- This file is part of VESTs (Vhdl tESTs).

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-- June 1991. A copy of this license agreement can be found in the file
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-- You should have received a copy of the GNU General Public License
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-- ---------------------------------------------------------------------
--
-- $Id: test178.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
-- $Revision: 1.1 $
--
-- ---------------------------------------------------------------------

----------------------------------------------------------------------
-- SIERRA REGRESSION TESTING MODEL
-- Develooped at:
-- Distriburted Processing Laboratory
-- University of Cincinnati
-- Cincinnati
----------------------------------------------------------------------
-- File          : test178.ams
-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
-- Created       : Sept 2001
----------------------------------------------------------------------
-- Description :
----------------------------------------------------------------------
-- the test is done for checking the correct implementation
-- of the simultaneous procedural equation statement.it checks
-- nature declaration, terminal and quantity declarations.

PACKAGE electricalSystem IS
    NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE;
    FUNCTION  SIN (X : real ) RETURN real;
    FUNCTION  EXP  (X : real ) RETURN real;
END PACKAGE electricalSystem;


USE work.electricalSystem.all;

ENTITY simproc IS
END simproc;

ARCHITECTURE asimproc OF simproc IS

    terminal T1: electrical;
    quantity vd across id through T1;
    quantity charge: real;
    constant vt: real:= 1.0;
BEGIN
        eq1: vd==1.0;
	proc1: procedural is
	variable vres:real;
	constant tau:real:=1.0;
	variable ares: real;
	begin
		e1: ares:=vd*1.0;
		e3: vres:=vt;
        end procedural;

END asimproc ;