-- Copyright (C) 2001-2002 The University of Cincinnati.  
-- All rights reserved. 

-- This file is part of VESTs (Vhdl tESTs).

-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
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-- You may modify, distribute, and use the software contained in this
-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
-- June 1991. A copy of this license agreement can be found in the file
-- "COPYING", distributed with this archive.

-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 

-- ---------------------------------------------------------------------
--
-- $Id: test117.ams,v 1.1 2002-03-27 22:11:18 paw Exp $
-- $Revision: 1.1 $
--
-- ---------------------------------------------------------------------

----------------------------------------------------------------------
-- SIERRA REGRESSION TESTING MODEL
-- Develooped at:
-- Distriburted Processing Laboratory
-- University of Cincinnati
-- Cincinnati
----------------------------------------------------------------------
-- File          : test117.ams
-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
-- Created       : May 2001
----------------------------------------------------------------------
-- Description :
----------------------------------------------------------------------
-- the test checks the correctness of the subtype usage and also
-- checks for the tolerance aspect associated with the subtype.
----------------------------------------------------------------------

Package electricalsystem is
 FUNCTION SIN(X : real) RETURN real;

subtype voltage is real tolerance "default_voltage=1.0e-3";
subtype current is real; -- tolerance "default_current= 1.0e-4";
subtype resistance is real;

nature electrical is voltage across current through ground reference;
end package electricalsystem;

use work.electricalsystem.all;

entity test is
end entity;

architecture atest of test is
--subtype voltage is real tolerance "default_voltage=1.0e-3";
--subtype current is real; -- tolerance "default_current= 1.0e-4";
subtype resistance is real;

nature electrical is voltage across current through;

terminal t1, t2: electrical;
quantity vr tolerance across ir through t1 to t2;
quantity vs across t1;
--quantity vout across t2;

begin
e1: vs==5.0 *sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12);

e2: vr==ir*1.0;

end architecture;