-- Copyright (C) 2000-2002 The University of Cincinnati.  
-- All rights reserved. 

-- This file is part of VESTs (Vhdl tESTs).

-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
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-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.

-- By using or copying this Software, Licensee agrees to abide by the
-- intellectual property laws, and all other applicable laws of the U.S.,
-- and the terms of this license.

-- You may modify, distribute, and use the software contained in this
-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
-- June 1991. A copy of this license agreement can be found in the file
-- "COPYING", distributed with this archive.

-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 

-- ---------------------------------------------------------------------
--
-- $Id: above_attr.ams,v 1.1 2002-03-27 22:11:17 paw Exp $
-- $Revision: 1.1 $
--
-- ---------------------------------------------------------------------

PACKAGE electricalSystem IS
    NATURE electrical IS real ACROSS real THROUGH ground reference;
   -- NATURE electrical IS real ACROSS real THROUGH;
    FUNCTION SIN(X : real) RETURN real;
    FUNCTION EXP(X : real) RETURN real;
    FUNCTION SQRT(X : real) RETURN real;
    FUNCTION POW(X,Y : real) RETURN real;

    --ALIAS GND is electrical'reference;
END PACKAGE electricalSystem;

use work.electricalSystem.all;
use std.textio.all;
entity test is
end entity;

architecture atest of test is
  constant R1: real :=10.0;
  constant R2: real :=5.0;
  terminal T1,T2:electrical;
  quantity V1 across I1 through T1 to T2;
  quantity V2 across I2 through T2;
  quantity VS across T1;
  quantity rt:real;
  signal ABSIG,o:boolean;
  --signal y:bit;

begin


ABSIG<=V1'above(V2+1.0);
            
 testbench:PROCESS
        VARIABLE outline : LINE;
        VARIABLE Headline   : string(1 TO 33) :=
            "time ABSIG";
        VARIABLE   seperator    : string(1 TO 1) := " ";
        VARIABLE   flag     : bit := '0';
        VARIABLE tmp:bit;
        FILE outfile: text OPEN WRITE_MODE IS "above_attr.out";
    BEGIN
        IF (flag = '0') THEN
            flag := '1';
            WRITE(outline,Headline);
            WRITELINE(outfile,outline);
        ELSE
            WRITE(outline, now);
            WRITE(outline,seperator);
            IF (ABSIG = true) THEN
            tmp:='1';
            ELSE
            tmp:='0';
            WRITE(outline,tmp);
            END IF;
            WRITE(outline,seperator);
            writeline(outfile,outline);
        END IF;
        WAIT ON ABSIG;
    END PROCESS;

e1:      V1 == I1*R1;
e2:      V2 == I2*R2;
esource: VS == 5.0 * sin(2.0 * 3.141592 *100.0 * real(time'pos(now))*1.0e-15);

END ARCHITECTURE atest;