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-- All rights reserved. 

-- This file is part of VESTs (Vhdl tESTs).

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-- June 1991. A copy of this license agreement can be found in the file
-- "COPYING", distributed with this archive.

-- You should have received a copy of the GNU General Public License
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-- ---------------------------------------------------------------------
--
-- $Id: test186.ams,v 1.2 2003-08-05 15:14:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------

PACKAGE electricalSystem IS
    subtype voltage is real ;
    subtype current is real ;

   NATURE electrical IS voltage ACROSS current THROUGH Ground reference;
   --NATURE electrical IS real ACROSS real THROUGH Ground reference;
   NATURE electrical_vector is array(natural range<>) of electrical ;
   --type real_vector is array(natural range<>) of voltage ;
   subnature el_vec is electrical_vector(0 to 100);
   FUNCTION SIN(X : real) RETURN real;
END PACKAGE electricalSystem;

use work.electricalsystem.all;
  
--entity declaration

ENTITY RLC IS
   
END RLC;

--architecture declaration

ARCHITECTURE behavior  OF RLC IS

    
   terminal n1 : electrical; 
   terminal n2: el_vec;
   
   quantity vr1 across ir1 through n1 to n2;
   quantity vr2 across ir2 through n2 to ground;
   quantity vs across n1 ;
   constant r1 : REAL := 20.0;
   constant r2 : REAL := 10.0;


BEGIN

res1 : vr1 == ir1 * r1;
res2 : vr2 == ir2 * r2;
vsrc : vs  == 5.0 * sin(2.0 * 3.1415 * 10.0 --sine source
                              * real(time'pos(now)) * 1.0e-9);

END architecture behavior;