From 6c3f709174e8e4d5411f851cedb7d84c38d3b04a Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Fri, 20 Dec 2013 04:48:54 +0100 Subject: Import vests testsuite --- .../ashenden/compliant/misc-topics/SR_flipflop.vhd | 41 ++++++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/SR_flipflop.vhd (limited to 'testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/SR_flipflop.vhd') diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/SR_flipflop.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/SR_flipflop.vhd new file mode 100644 index 0000000..863f9e9 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/SR_flipflop.vhd @@ -0,0 +1,41 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity SR_flipflop is + port ( s_n, r_n : in bit; q, q_n : inout bit ); + +begin + + postponed process (q, q_n) is + begin + assert now = 0 fs or q = not q_n + report "implementation error: q /= not q_n"; + end postponed process; + +end entity SR_flipflop; + +-------------------------------------------------- + +architecture dataflow of SR_flipflop is +begin + + gate_1 : q <= s_n nand q_n; + gate_2 : q_n <= r_n nand q; + +end architecture dataflow; -- cgit