From 6c3f709174e8e4d5411f851cedb7d84c38d3b04a Mon Sep 17 00:00:00 2001
From: Tristan Gingold
Date: Fri, 20 Dec 2013 04:48:54 +0100
Subject: Import vests testsuite

---
 .../ad-hoc/fromUC/regression_test/test184.ams      | 110 +++++++++++++++++++++
 1 file changed, 110 insertions(+)
 create mode 100644 testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test184.ams

(limited to 'testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test184.ams')

diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test184.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test184.ams
new file mode 100644
index 0000000..ad706e0
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test184.ams
@@ -0,0 +1,110 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test184.ams,v 1.2 2003-08-05 15:14:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+---------------------------------------------------------------------
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test100.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : Sept 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- half wave Rectifier model ...
+-- the test is done for checking the correct implementation
+-- of the simultaneous if statement.it checks
+-- nature declaration, terminal and quantity declarations.
+
+----------------------------------------------------------------------
+--     T1   diode D  T2    
+--     o-----|>|-----o-------o       The circuit comprises:
+--     |             |               i)  A diode .
+--    ( )            >R=100ohms      ii) A sinusoidal voltage source.
+--     |Vs = 5sinwt  >               iii)A resistor R.
+--     |             >
+--     |_____________|_______o
+--                   |gnd
+--                 -----
+----------------------------------------------------------------------
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH ground REFERENCE;
+    FUNCTION  SIN (X : real ) RETURN real;
+    FUNCTION  EXP  (X : real ) RETURN real;
+END PACKAGE electricalSystem;
+
+----------------------------------------------------------------------
+
+USE work.electricalSystem.all;
+
+ENTITY hwr IS
+END hwr;
+
+ARCHITECTURE ahwr OF hwr IS
+
+    terminal T1, T2 : electrical;
+    quantity VDiode across IDiode through T1 to T2;
+    quantity V2 across I2 through T2 ;
+    quantity VS across T1 ;
+
+    CONSTANT saturation_current : real := 0.0000000000001;
+    CONSTANT Vt : real := 0.025;
+        
+    CONSTANT BV : real := 100.0;
+    CONSTANT neg_sat : real := -saturation_current;
+    
+BEGIN  
+
+      --diode equations
+      if( vDiode >= (-1.0 * Vt)) USE
+        eq1: iDiode == saturation_current * (exp(vDiode/Vt) - 1.0);
+
+      ELSIF ((vDiode < (-3.0 * Vt)) AND (vDiode > -BV)) use
+        eq2:  iDiode == neg_sat;
+
+      ELSE
+        eq3: iDiode == neg_sat * (exp(-(BV + vDiode)/Vt) - 1.0 +
+                                    saturation_current);
+      END USE ;
+                                                       
+      eqn2: v2 == 100.0 * i2;
+    
+      eqn4: vs == 5.0 * sin(2.0 * 3.14 * 100000.0 *
+                            real(time'pos(now)) * 1.0e-15 );
+    
+END ahwr ;
-- 
cgit