From 6c3f709174e8e4d5411f851cedb7d84c38d3b04a Mon Sep 17 00:00:00 2001
From: Tristan Gingold
Date: Fri, 20 Dec 2013 04:48:54 +0100
Subject: Import vests testsuite

---
 .../functional/signals/assign/simple-array-assign.vhdl   | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)
 create mode 100644 testsuite/vests/vhdl-93/clifton-labs/compliant/functional/signals/assign/simple-array-assign.vhdl

(limited to 'testsuite/vests/vhdl-93/clifton-labs/compliant/functional/signals/assign/simple-array-assign.vhdl')

diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/signals/assign/simple-array-assign.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/signals/assign/simple-array-assign.vhdl
new file mode 100644
index 0000000..d3809c5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/signals/assign/simple-array-assign.vhdl
@@ -0,0 +1,16 @@
+entity test_bench is
+end test_bench;
+
+architecture only of test_bench is
+  signal sig : bit_vector( 3 downto 0 );
+begin  -- only
+  p: process
+  begin  -- process p
+    sig <= "1001";
+    wait for 1 fs;
+    assert sig = "1001" report "TEST FAILED" severity FAILURE;
+    report "TEST PASSED" severity NOTE;
+    wait;
+  end process p;
+    
+end only;
-- 
cgit