From 6c3f709174e8e4d5411f851cedb7d84c38d3b04a Mon Sep 17 00:00:00 2001
From: Tristan Gingold
Date: Fri, 20 Dec 2013 04:48:54 +0100
Subject: Import vests testsuite

---
 .../components/unconstrained-array-example.vhdl    | 47 ++++++++++++++++++++++
 1 file changed, 47 insertions(+)
 create mode 100644 testsuite/vests/vhdl-93/clifton-labs/compliant/functional/components/unconstrained-array-example.vhdl

(limited to 'testsuite/vests/vhdl-93/clifton-labs/compliant/functional/components/unconstrained-array-example.vhdl')

diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/components/unconstrained-array-example.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/components/unconstrained-array-example.vhdl
new file mode 100644
index 0000000..1a021e3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/components/unconstrained-array-example.vhdl
@@ -0,0 +1,47 @@
+entity forty_two is
+  port (
+    bv_out : out bit_vector );
+end forty_two;
+
+architecture only of forty_two is
+begin  -- only
+  process
+  begin  -- process
+    bv_out <= "0110";
+    wait;
+  end process;
+end only;
+
+entity test_bench is
+end test_bench;
+
+architecture only of test_bench is
+
+  component forty_two_component
+    port (
+      c_bv_out : out bit_vector );
+  end component;
+
+  for ft0 : forty_two_component
+    use entity work.forty_two(only)
+      port map (
+        bv_out => c_bv_out );
+  
+  signal bv_signal : bit_vector( 3 downto 0 );
+
+begin  -- only
+
+  ft0 : component forty_two_component
+    port map (
+      c_bv_out => bv_signal );
+
+
+  test: process
+  begin  -- process test
+    wait for 1 ms;
+    assert bv_signal = "0110" report "TEST FAILED" severity ERROR;
+    assert not(bv_signal = "0110") report "TEST PASSED" severity NOTE;
+    wait;
+  end process test;
+  
+end only;
-- 
cgit