From 6c3f709174e8e4d5411f851cedb7d84c38d3b04a Mon Sep 17 00:00:00 2001
From: Tristan Gingold
Date: Fri, 20 Dec 2013 04:48:54 +0100
Subject: Import vests testsuite

---
 .../components/integer-default-binding.vhdl        | 41 ++++++++++++++++++++++
 1 file changed, 41 insertions(+)
 create mode 100644 testsuite/vests/vhdl-93/clifton-labs/compliant/functional/components/integer-default-binding.vhdl

(limited to 'testsuite/vests/vhdl-93/clifton-labs/compliant/functional/components/integer-default-binding.vhdl')

diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/components/integer-default-binding.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/components/integer-default-binding.vhdl
new file mode 100644
index 0000000..d162a11
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/components/integer-default-binding.vhdl
@@ -0,0 +1,41 @@
+entity forty_two is
+  port (
+    int_out : out integer);
+end forty_two;
+
+architecture only of forty_two is
+begin  -- only
+  process
+  begin  -- process
+    int_out <= 42;
+    wait;
+  end process;
+end only;
+
+entity test_bench is
+end test_bench;
+
+architecture only of test_bench is
+
+  component forty_two
+    port (
+      int_out : out integer);
+  end component;
+  
+  signal int_signal : integer;
+
+begin  -- only
+
+  ft0 : component forty_two
+    port map (
+      int_out => int_signal );
+
+  test: process
+  begin  -- process test
+    wait for 1 ms;
+    assert int_signal = 42 report "TEST FAILED" severity ERROR;
+    assert not(int_signal = 42) report "TEST PASSED" severity NOTE;
+    wait;
+  end process test;
+  
+end only;
-- 
cgit