From 8ab3c6e57e7f11eb79d1d7f948fb29a16225c9f2 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Tue, 13 Jan 2015 20:19:51 +0100 Subject: Add reproducer from ticket #32. --- testsuite/gna/ticket32/arith_prefix_and.vhdl | 95 ++++++++++++++++++++++ testsuite/gna/ticket32/arith_prefix_and_tb.vhdl | 95 ++++++++++++++++++++++ testsuite/gna/ticket32/muxcy.vhdl | 12 +++ testsuite/gna/ticket32/repro.vhdl | 10 +++ testsuite/gna/ticket32/simulation.vhdl | 102 ++++++++++++++++++++++++ testsuite/gna/ticket32/testsuite.sh | 20 +++++ 6 files changed, 334 insertions(+) create mode 100644 testsuite/gna/ticket32/arith_prefix_and.vhdl create mode 100644 testsuite/gna/ticket32/arith_prefix_and_tb.vhdl create mode 100644 testsuite/gna/ticket32/muxcy.vhdl create mode 100644 testsuite/gna/ticket32/repro.vhdl create mode 100644 testsuite/gna/ticket32/simulation.vhdl create mode 100755 testsuite/gna/ticket32/testsuite.sh (limited to 'testsuite/gna/ticket32') diff --git a/testsuite/gna/ticket32/arith_prefix_and.vhdl b/testsuite/gna/ticket32/arith_prefix_and.vhdl new file mode 100644 index 0000000..0faae5e --- /dev/null +++ b/testsuite/gna/ticket32/arith_prefix_and.vhdl @@ -0,0 +1,95 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +-- vim: tabstop=2:shiftwidth=2:noexpandtab +-- kate: tab-width 2; replace-tabs off; indent-width 2; +-- +-- ============================================================================= +-- Description: Prefix AND computation: y(i) <= '1' when x(i downto 0) = (i downto 0 => '1') else '0' +-- This implementation uses carry chains for wider implementations. +-- +-- Authors: Thomas B. Preusser +-- ============================================================================= +-- Copyright 2007-2014 Technische Universität Dresden - Germany +-- Chair for VLSI-Design, Diagnostics and Architecture +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library unisim; + + +entity arith_prefix_and is + generic ( + N : positive + ); + port ( + x : in std_logic_vector(N-1 downto 0); + y : out std_logic_vector(N-1 downto 0) + ); +end arith_prefix_and; + + +architecture rtl of arith_prefix_and is + type T_VENDOR is (VENDOR_XILINX, VENDOR_ALTERA); + + constant VENDOR : T_VENDOR := VENDOR_XILINX; + +begin + y(0) <= x(0); + gen1: if N > 1 generate + signal p : unsigned(N-1 downto 1); + begin + p(1) <= x(0) and x(1); + gen2: if N > 2 generate + p(N-1 downto 2) <= unsigned(x(N-1 downto 2)); + + -- Generic Carry Chain through Addition + genGeneric: if VENDOR /= VENDOR_XILINX generate + signal s : std_logic_vector(N downto 1); + begin + s <= std_logic_vector(('0' & p) + 1); + y(N-1 downto 2) <= s(N downto 3) xor ('0' & x(N-1 downto 3)); + end generate genGeneric; + + -- Direct Carry Chain by MUXCY Instantiation + genXilinx: if VENDOR = VENDOR_XILINX generate +-- component MUXCY +-- port ( +-- S : in std_logic; +-- DI : in std_logic; +-- CI : in std_logic; +-- O : out std_logic +-- ); +-- end component; + signal c : std_logic_vector(N-1 downto 0); + begin + c(0) <= '1'; + genChain: for i in 1 to N-1 generate + mux : entity unisim.MUXCY + port map ( + S => p(i), + DI => '0', + CI => c(i-1), + O => c(i) + ); + end generate genChain; + y(N-1 downto 2) <= c(N-1 downto 2); + end generate genXilinx; + + end generate gen2; + y(1) <= p(1); + end generate gen1; +end rtl; diff --git a/testsuite/gna/ticket32/arith_prefix_and_tb.vhdl b/testsuite/gna/ticket32/arith_prefix_and_tb.vhdl new file mode 100644 index 0000000..d566818 --- /dev/null +++ b/testsuite/gna/ticket32/arith_prefix_and_tb.vhdl @@ -0,0 +1,95 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +-- vim: tabstop=2:shiftwidth=2:noexpandtab +-- kate: tab-width 2; replace-tabs off; indent-width 2; +-- +-- ============================================================================= +-- Testbench: Testbench for arith_prefix_and. +-- +-- Authors: Thomas B. Preusser +-- +-- Description: +-- ------------------------------------ +-- Automated testbench for PoC.arith_prng +-- The Pseudo-Random Number Generator is instanziated for 8 bits. The +-- output sequence is compared to 256 precalculated values. +-- +-- License: +-- ============================================================================= +-- Copyright 2007-2014 Technische Universitaet Dresden - Germany +-- Chair for VLSI-Design, Diagnostics and Architecture +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +entity arith_prefix_and_tb is +end arith_prefix_and_tb; + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +library PoC; +use PoC.simulation.ALL; + + +architecture tb of arith_prefix_and_tb is + +-- component arith_prefix_and +-- generic ( +-- N : positive +-- ); +-- port ( +-- x : in std_logic_vector(N-1 downto 0); +-- y : out std_logic_vector(N-1 downto 0) +-- ); +-- end component; + + -- component generics + constant N : positive := 8; + + -- component ports + signal x : std_logic_vector(N-1 downto 0); + signal y : std_logic_vector(N-1 downto 0); + +begin -- tb + + -- component instantiation + DUT : entity PoC.arith_prefix_and + generic map ( + N => N + ) + port map ( + x => x, + y => y + ); + + -- Stimuli + process + begin + -- Exhaustive Testing + for i in 0 to 2**N-1 loop + x <= std_logic_vector(to_unsigned(i, N)); + wait for 10 ns; + for j in 0 to N-1 loop + tbAssert((y(j) = '1') = (x(j downto 0) = (j downto 0 => '1')), + "Wrong result for "&integer'image(i)&" / "&integer'image(j)); + end loop; + end loop; + + -- Report overall result + tbPrintResult; + + wait; -- forever + end process; + +end tb; diff --git a/testsuite/gna/ticket32/muxcy.vhdl b/testsuite/gna/ticket32/muxcy.vhdl new file mode 100644 index 0000000..d9c912f --- /dev/null +++ b/testsuite/gna/ticket32/muxcy.vhdl @@ -0,0 +1,12 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity muxcy is + port (s, di, ci : std_logic; + o : out std_logic); +end muxcy; + +architecture behav of muxcy is +begin + o <= di when s = '0' else ci; +end behav; diff --git a/testsuite/gna/ticket32/repro.vhdl b/testsuite/gna/ticket32/repro.vhdl new file mode 100644 index 0000000..277fa3f --- /dev/null +++ b/testsuite/gna/ticket32/repro.vhdl @@ -0,0 +1,10 @@ +entity repro is +end; + +architecture tb of repro is + signal x : bit_vector(1 downto 0); + signal y : bit; +begin + assert (y = '1') = (x = "11"); +end tb; + diff --git a/testsuite/gna/ticket32/simulation.vhdl b/testsuite/gna/ticket32/simulation.vhdl new file mode 100644 index 0000000..ee4c382 --- /dev/null +++ b/testsuite/gna/ticket32/simulation.vhdl @@ -0,0 +1,102 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +-- vim: tabstop=2:shiftwidth=2:noexpandtab +-- kate: tab-width 2; replace-tabs off; indent-width 2; +-- +-- ============================================================================= +-- Testbench: Simulation constants, functions and utilities. +-- +-- Authors: Patrick Lehmann +-- Thomas B. Preusser +-- +-- Description: +-- ------------------------------------ +-- TODO +-- +-- License: +-- ============================================================================= +-- Copyright 2007-2014 Technische Universitaet Dresden - Germany +-- Chair for VLSI-Design, Diagnostics and Architecture +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; + +package simulation is + --+ Test Bench Status Management ++++++++++++++++++++++++++++++++++++++++++ + + --* The testbench is marked as failed. If a message is provided, it is + --* reported as an error. + procedure tbFail(msg : in string := ""); + + --* If the passed condition has evaluated false, the testbench is marked + --* as failed. In this case, the optional message will be reported as an + --* an error if one was provided. + procedure tbAssert(cond : in boolean; msg : in string := ""); + + --* Prints out the overall testbench result as defined by the automated + --* testbench process. Unless tbFail() or tbAssert() with a false condition + --* have been called before, a successful completion will be reported, a + --* failure otherwise. + procedure tbPrintResult; + + -- TODO: integrate VCD simulation functions and procedures from sim_value_change_dump.vhdl here + + -- checksum functions + -- =========================================================================== + -- TODO: move checksum functions here +end; + + +use std.TextIO.all; + +package body simulation is + + --+ Test Bench Status Management ++++++++++++++++++++++++++++++++++++++++++ + + --* Internal state variable to log a failure condition for final reporting. + --* Once de-asserted, this variable will never return to a value of true. + shared variable pass : boolean := true; + + procedure tbFail(msg : in string := "") is + begin + if msg'length > 0 then + report msg severity error; + end if; + pass := false; + end; + + procedure tbAssert(cond : in boolean; msg : in string := "") is + begin + if not cond then + tbFail(msg); + end if; + end; + + procedure tbPrintResult is + variable l : line; + begin + write(l, string'("SIMULATION RESULT = ")); + if pass then + write(l, string'("PASSED")); + else + write(l, string'("FAILED")); + end if; + writeline(output, l); + end procedure; + + -- checksum functions + -- =========================================================================== + +end package body; diff --git a/testsuite/gna/ticket32/testsuite.sh b/testsuite/gna/ticket32/testsuite.sh new file mode 100755 index 0000000..2ccc0ce --- /dev/null +++ b/testsuite/gna/ticket32/testsuite.sh @@ -0,0 +1,20 @@ +#! /bin/sh + +. ../../testenv.sh + +analyze repro.vhdl +elab_simulate repro + +clean + +analyze --work=unisim muxcy.vhdl +analyze --work=poc simulation.vhdl +analyze --work=poc arith_prefix_and.vhdl +analyze --work=test arith_prefix_and_tb.vhdl +elab_simulate --work=test arith_prefix_and_tb + +clean unisim +clean poc +clean test + +echo "Test successful" -- cgit