From 212268f54c947f4360a7d0e5b45faa97f76a4a9d Mon Sep 17 00:00:00 2001
From: Tristan Gingold
Date: Sat, 21 Jun 2014 21:24:15 +0200
Subject: Add psl cover directive (ticket19).

---
 testsuite/gna/ticket19/psl_test_cover.vhd | 53 +++++++++++++++++++++++++++++++
 1 file changed, 53 insertions(+)
 create mode 100644 testsuite/gna/ticket19/psl_test_cover.vhd

(limited to 'testsuite/gna/ticket19/psl_test_cover.vhd')

diff --git a/testsuite/gna/ticket19/psl_test_cover.vhd b/testsuite/gna/ticket19/psl_test_cover.vhd
new file mode 100644
index 0000000..4f3666f
--- /dev/null
+++ b/testsuite/gna/ticket19/psl_test_cover.vhd
@@ -0,0 +1,53 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+
+entity psl_test_cover is
+end entity psl_test_cover;
+
+
+architecture test of psl_test_cover is
+
+
+  signal s_rst_n : std_logic := '0';
+  signal s_clk   : std_logic := '0';
+  signal s_write : std_logic;
+  signal s_read  : std_logic;
+
+
+begin
+
+
+  s_rst_n <= '1' after 100 ns;
+  s_clk   <= not s_clk after 10 ns;
+
+
+  TestP : process is
+  begin
+    report "RUNNING PSL_TEST_COVER test case";
+    report "================================";
+    s_write <= '0';
+    s_read  <= '0';
+    wait until s_rst_n = '1' and rising_edge(s_clk);
+    s_write <= '1';  -- cover should hit
+    wait until rising_edge(s_clk);
+    s_read  <= '1';  -- assertion should hit
+    wait until rising_edge(s_clk);
+    s_write <= '0';
+    s_read  <= '0';
+    wait;
+  end process TestP;
+
+
+
+  -- psl statements
+
+  -- psl default clock is rising_edge(s_clk);
+
+  -- cover directive seems not supported (ignored by GHDL)
+  -- psl cover always (s_write -> not(s_read));
+
+
+end architecture test;
\ No newline at end of file
-- 
cgit