ghdl/.git - VHDL 2008/93/87 simulator

Age	Commit message (Collapse)	Author
2015-01-18	Style fixes.	Tristan Gingold

2015-01-18	simulation: adjust for vhdl08 configurations.	Tristan Gingold

2015-01-18	execution: fix v87 concat with element.	Tristan Gingold

2015-01-17	simulation: handle v87 concatenation.	Tristan Gingold

2015-01-17	debugger: add list command.	Tristan Gingold

2015-01-17	ghdlsimul: adjust after use of name for block_specification.	Tristan Gingold

2015-01-16	Fix build of ghdl_simul (WIP).	Tristan Gingold

2015-01-16	Keep and handle simple name for Block_Specification.	Tristan Gingold

2015-01-16	disp_tree: add Max_Depth to limit recursion.	Tristan Gingold

2015-01-16	canon: fix after previous change (do not generate default config for for-gen)	Tristan Gingold

2015-01-15	PSL: add comments, scan endpoint.	Tristan Gingold

2015-01-15	Evaluation: implement array compare for discrete arrays.	Tristan Gingold

2015-01-15	Create the Sem_Qualified_Expression function.	Tristan Gingold

2015-01-15	parser: improve error message and recovery on = for default expression.	Tristan Gingold

2015-01-15	Evaluation: implement array comparaison (greater or less).	Tristan Gingold

2015-01-14	xrefs: adjust for vhdl08.	Tristan Gingold

2015-01-14	disp_vhdl: adjust for vhdl2008 (generate, bit string).	Tristan Gingold

2015-01-12	sem: fix Can_Collapse_Signals regression.	Tristan Gingold

2015-01-12	grt: improve --disp-signals-table output.	Tristan Gingold

2015-01-12	vhdl2008: expanded names in for-generate statements.	Tristan Gingold

2015-01-12	vhdl2008: handle expanded names in if-generate statements.	Tristan Gingold

2015-01-11	Fix ticket #29: add instance label in created symbols name.	Tristan Gingold

2015-01-10	Handle overflow during evaluation of type conversion. Forward on 'image.	Tristan Gingold

2015-01-10	vhdl08: forbid simple block_specification for labeled if-generate statement.	Tristan Gingold

2015-01-10	vhdl08: block configuration for if-generate statements.	Tristan Gingold

2015-01-08	Canon: do not free old concurrent statement.	Tristan Gingold

2015-01-07	Handle vhdl08 if generate statements	Tristan Gingold

2015-01-04	Rework for vhdl08 generate: change rtis.	Tristan Gingold

2015-01-03	Initial rework for vhdl 2008 generate statements.	Tristan Gingold

2014-12-31	Rename name_table.name_buffer and name_length to avoid clash.	Tristan Gingold

2014-12-30	Improve error recovery.	Tristan Gingold

2014-12-30	vhdl 2008: handle sized bit strings.	Tristan Gingold

2014-12-29	Rework string literals: store literals position.	Tristan Gingold

2014-12-26	Optimize scan_identifier.	Tristan Gingold

2014-12-26	Rewrite sem_scopes tables for speed-up (and clarification).	Tristan Gingold

2014-12-24	evaluation.adb: style changes.	Tristan Gingold

2014-12-23	configuration.adb: change for style.	Tristan Gingold

2014-12-23	Fix ghdl -m for jit: handle multiple libraries.	Tristan Gingold

2014-12-22	Add comments.	Tristan Gingold

2014-12-22	Reduce size of library_declaration.	Tristan Gingold

2014-12-16	Recognize some ieee.std_logic_1164 functions.	Tristan Gingold

2014-12-16	translation: give full path for to debug filename.	Tristan Gingold

2014-12-15	Use same node for implicit and explicit subprogram declarations.	Tristan Gingold

2014-12-14	Reduce size of configuration declaration and guard signal declaration.	Tristan Gingold

2014-12-14	reduce size of enumeration_literal.	Tristan Gingold

2014-12-14	iirs: reduce size of interface objects.	Tristan Gingold

2014-12-14	iirs: reduce size of signal_declaration.	Tristan Gingold

2014-12-14	iirs: reduce memory size.	Tristan Gingold

2014-12-14	Put attribute_value_chain in parent.	Tristan Gingold

2014-12-13	iirs: move delay_mechanism to flag1; adjust xtools/pnodes.py for new sources.	Tristan Gingold