ghdl/.git - VHDL 2008/93/87 simulator

Age	Commit message (Collapse)	Author
2015-12-18	Pass signal values to interfaces. 'sigptr' optimization.	Tristan Gingold
	Improve simulation speed by about 20%.
2015-09-15	trans-rtis: fix uninitialized field (that could result in a crash).	Tristan Gingold

2015-08-29	Replace fat accesses by bounds accesses	Tristan Gingold
	translate: separate info for signals from object. Improve some error messages.
2015-01-07	Handle vhdl08 if generate statements	Tristan Gingold

2015-01-04	Rework for vhdl08 generate: change rtis.	Tristan Gingold

2015-01-03	Initial rework for vhdl 2008 generate statements.	Tristan Gingold

2014-12-31	Rename name_table.name_buffer and name_length to avoid clash.	Tristan Gingold

2014-12-15	Use same node for implicit and explicit subprogram declarations.	Tristan Gingold

2014-12-14	iirs: reduce size of signal_declaration.	Tristan Gingold

2014-12-13	rtis: add source location for blocks and object. Use them in fst dumper.	Tristan Gingold

2014-11-09	Split translation into child packages.	Tristan Gingold