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VHDL 2008/93/87 simulator
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trans-chap9.adb
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2015-12-18
Pass signal values to interfaces. 'sigptr' optimization.
Tristan Gingold
Improve simulation speed by about 20%.
2015-09-04
Suppress stack switching; save process state in secondary stack.
Tristan Gingold
2015-09-02
Translate: explicitly clean transient types.
Tristan Gingold
2015-08-29
Allow allocators in default value of subprograms
Tristan Gingold
(Handle them in are_trees_equal).
2015-08-29
Replace fat accesses by bounds accesses
Tristan Gingold
translate: separate info for signals from object. Improve some error messages.
2015-06-05
Rework procedure calls, now use a record to pass parameters.
Tristan Gingold
2015-03-31
Fix entity instantiation with extended identifier.
Tristan Gingold
From a patch by Ole Myren Rohne.
2015-01-16
Keep and handle simple name for Block_Specification.
Tristan Gingold
2015-01-11
Fix ticket #29: add instance label in created symbols name.
Tristan Gingold
2015-01-07
Handle vhdl08 if generate statements
Tristan Gingold
2015-01-04
Rework for vhdl08 generate: change rtis.
Tristan Gingold
2015-01-03
Initial rework for vhdl 2008 generate statements.
Tristan Gingold
2014-11-20
trans-chap9: fix invalid generation of ortho code.
Tristan Gingold
2014-11-09
Split translation into child packages.
Tristan Gingold