ghdl/.git - VHDL 2008/93/87 simulator

Age	Commit message (Collapse)	Author
2015-01-10	Handle overflow during evaluation of type conversion. Forward on 'image.	Tristan Gingold

2014-12-31	Rename name_table.name_buffer and name_length to avoid clash.	Tristan Gingold

2014-12-29	Rework string literals: store literals position.	Tristan Gingold

2014-12-16	Recognize some ieee.std_logic_1164 functions.	Tristan Gingold

2014-12-15	Use same node for implicit and explicit subprogram declarations.	Tristan Gingold

2014-12-14	reduce size of enumeration_literal.	Tristan Gingold

2014-11-29	Allow -frelaxed-rules for v87 designs	Tristan Gingold

2014-11-22	Gen_Call_Type_Builder: use Mnode.	Tristan Gingold

2014-11-21	concatenation: remove unused left over.	Tristan Gingold

2014-11-17	Translate: rewrite concatenation. Now O(n).	Tristan Gingold

2014-11-16	Translate_Range: use mnodes.	Tristan Gingold

2014-11-16	Translate_Range_Expression_Ptr: use Mnode and rename.	Tristan Gingold

2014-11-15	Translate_Reverse_Range_Ptr: use mnode instead of ptr and rename.	Tristan Gingold

2014-11-15	translate_expression: handle implicit type for aggregate.	Tristan Gingold

2014-11-11	Create_Range_From_Length: use Mnode instead of ptr. Style changes.	Tristan Gingold

2014-11-11	Style changes.	Tristan Gingold

2014-11-09	Split translation into child packages.	Tristan Gingold