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VHDL 2008/93/87 simulator
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iirs.adb
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2016-01-16
Add support for conditional assignments.
Tristan Gingold
2016-01-11
Set type staticness for a constant declaration and attribute specification.
Tristan Gingold
Fix for issue 10.
2015-09-02
Translate: explicitly clean transient types.
Tristan Gingold
2015-06-07
Add suspend_flag.
Tristan Gingold
2015-05-26
Rework of overload resolution in implicit conversions.
Tristan Gingold
Fix tiket 81.
2015-05-23
Preliminary work to support external names (parse, semantic)
Tristan Gingold
2015-05-16
Give priority to function calls without implicit conversion.
Tristan Gingold
Fix ticket 64.
2015-05-13
Change library format: now store file checksum instead of file time stamp.
Tristan Gingold
For ticket 48.
2015-05-12
Add context declaration and reference (vhdl 2008).
Tristan Gingold
2015-01-12
vhdl2008: handle expanded names in if-generate statements.
Tristan Gingold
2015-01-10
vhdl08: forbid simple block_specification for labeled if-generate statement.
Tristan Gingold
2015-01-03
Initial rework for vhdl 2008 generate statements.
Tristan Gingold
2014-12-30
vhdl 2008: handle sized bit strings.
Tristan Gingold
2014-12-29
Rework string literals: store literals position.
Tristan Gingold
2014-12-22
Reduce size of library_declaration.
Tristan Gingold
2014-12-15
Use same node for implicit and explicit subprogram declarations.
Tristan Gingold
2014-12-14
Reduce size of configuration declaration and guard signal declaration.
Tristan Gingold
2014-12-14
reduce size of enumeration_literal.
Tristan Gingold
2014-12-14
iirs: reduce size of interface objects.
Tristan Gingold
2014-12-14
iirs: reduce size of signal_declaration.
Tristan Gingold
2014-12-14
iirs: reduce memory size.
Tristan Gingold
2014-12-14
Put attribute_value_chain in parent.
Tristan Gingold
2014-12-13
iirs: move delay_mechanism to flag1; adjust xtools/pnodes.py for new sources.
Tristan Gingold
2014-11-04
Create src/vhdl subdirectory.
Tristan Gingold