diff options
Diffstat (limited to 'testsuite/vests/vhdl-ams/ashenden/compliant/packages')
23 files changed, 1359 insertions, 0 deletions
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/packages/address_decoder.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/address_decoder.vhd new file mode 100644 index 0000000..14c20b0 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/address_decoder.vhd @@ -0,0 +1,56 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity address_decoder is + port ( addr : in work.cpu_types.address; + status : in work.cpu_types.status_value; + mem_sel, int_sel, io_sel : out bit ); +end entity address_decoder; + +-------------------------------------------------- + +architecture functional of address_decoder is + + constant mem_low : work.cpu_types.address := X"000000"; + constant mem_high : work.cpu_types.address := X"EFFFFF"; + constant io_low : work.cpu_types.address := X"F00000"; + constant io_high : work.cpu_types.address := X"FFFFFF"; + +begin + + mem_decoder : + mem_sel <= '1' when ( work.cpu_types."="(status, work.cpu_types.fetch) + or work.cpu_types."="(status, work.cpu_types.mem_read) + or work.cpu_types."="(status, work.cpu_types.mem_write) ) + and addr >= mem_low + and addr <= mem_high else + '0'; + + int_decoder : + int_sel <= '1' when work.cpu_types."="(status, work.cpu_types.int_ack) else + '0'; + + io_decoder : + io_sel <= '1' when ( work.cpu_types."="(status, work.cpu_types.io_read) + or work.cpu_types."="(status, work.cpu_types.io_write) ) + and addr >= io_low + and addr <= io_high else + '0'; + +end architecture functional; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/packages/analog_output_interface.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/analog_output_interface.vhd new file mode 100644 index 0000000..604a989 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/analog_output_interface.vhd @@ -0,0 +1,77 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- not in book + + +library ieee; use ieee.std_logic_1164.all; +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity analog_output_interface is + port ( signal wr : in std_ulogic; + signal data : std_ulogic_vector(7 downto 0); + terminal analog_out : electrical ); +end entity analog_output_interface; + + +---------------- + + +library ieee; use ieee.std_logic_1164.all; +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity analog_interface_dac is + port ( signal d_in : std_ulogic_vector(7 downto 0); + terminal output : electrical; + terminal plus_supply, minus_supply : electrical ); +end entity analog_interface_dac; + + +architecture macroblock of analog_interface_dac is + +begin + +end architecture macroblock; + +-- end not in book + + + + +architecture structural of analog_output_interface is + + -- This architecture implements the interface as a register connected to a DAC. + -- NOTE: it uses the analog power supply terminals from clock_power_pkg + -- to supply the DAC. + + signal register_out : -- . . .; + -- not in book + std_ulogic_vector(7 downto 0); + -- end not in book + +begin + + -- ... + + dac : entity work.analog_interface_dac(macroblock) + port map ( d_in => register_out, output => analog_out, + plus_supply => work.clock_power_pkg.analog_plus_supply, + minus_supply => work.clock_power_pkg.analog_ground ); + +end architecture structural; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/packages/bit_vector_signed_arithmetic.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/bit_vector_signed_arithmetic.vhd new file mode 100644 index 0000000..80ce3c0 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/bit_vector_signed_arithmetic.vhd @@ -0,0 +1,78 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +package bit_vector_signed_arithmetic is + + function "+" ( bv1, bv2 : bit_vector ) return bit_vector; + + function "-" ( bv : bit_vector ) return bit_vector; + + function "*" ( bv1, bv2 : bit_vector ) return bit_vector; + + -- . . . + +end package bit_vector_signed_arithmetic; + +-------------------------------------------------- + +-- not in book +library ieee; use ieee.numeric_bit.all; +-- end not in book + +package body bit_vector_signed_arithmetic is + + function "+" ( bv1, bv2 : bit_vector ) return bit_vector is -- . . . + -- not in book + begin + return bit_vector( "+"(signed(bv1), signed(bv2)) ); + end function "+"; + -- end not in book + + function "-" ( bv : bit_vector ) return bit_vector is -- . . . + -- not in book + begin + return bit_vector( "-"(signed(bv)) ); + end function "-"; + -- end not in book + + function mult_unsigned ( bv1, bv2 : bit_vector ) return bit_vector is + -- . . . + begin + -- not in book + -- . . . + return bit_vector( "*"(unsigned(bv1), unsigned(bv2)) ); + -- end not in book + end function mult_unsigned; + + function "*" ( bv1, bv2 : bit_vector ) return bit_vector is + begin + if bv1(bv1'left) = '0' and bv2(bv2'left) = '0' then + return mult_unsigned(bv1, bv2); + elsif bv1(bv1'left) = '0' and bv2(bv2'left) = '1' then + return -mult_unsigned(bv1, -bv2); + elsif bv1(bv1'left) = '1' and bv2(bv2'left) = '0' then + return -mult_unsigned(-bv1, bv2); + else + return mult_unsigned(-bv1, -bv2); + end if; + end function "*"; + + -- . . . + +end package body bit_vector_signed_arithmetic; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/packages/bus_sequencer-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/bus_sequencer-1.vhd new file mode 100644 index 0000000..fda35f2 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/bus_sequencer-1.vhd @@ -0,0 +1,79 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- not in book + +library ieee; use ieee.std_logic_1164.all; + +entity bus_sequencer is + port ( rd, wr, sel, width, burst : out std_ulogic; + addr_low_4 : out std_ulogic_vector(3 downto 0); + ready : out std_ulogic; + control_reg_wr, status_reg_rd, data_fifo_wr, data_fifo_rd, + analog_out_wr_0, + other_signal : out std_ulogic ); +end entity bus_sequencer; + +---------------- + +library ieee; use ieee.std_logic_1164.all; + +entity state_register is + port ( phi1, phi2 : in std_ulogic; + next_state : in std_ulogic_vector(3 downto 0); + current_state : out std_ulogic_vector(3 downto 0) ); +end entity state_register; + + +architecture std_cell of state_register is + +begin + +end architecture std_cell; + +-- end not in book + + + + +architecture fsm of bus_sequencer is + + -- This architecture implements the sequencer as a finite-state machine. + -- NOTE: it uses the clock signals from clock_power_pkg to synchronize the fsm. + + signal next_state_vector : -- . . .; + -- not in book + std_ulogic_vector(3 downto 0); + signal current_state_vector : std_ulogic_vector(3 downto 0); + -- end not in book + +begin + + bus_sequencer_state_register : entity work.state_register(std_cell) + port map ( phi1 => work.clock_power_pkg.clock_phase1, + phi2 => work.clock_power_pkg.clock_phase2, + next_state => next_state_vector, + -- . . . ); + -- not in book + current_state => current_state_vector ); + -- end not in book + + -- . . . + +end architecture fsm; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/packages/clock_power_pkg.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/clock_power_pkg.vhd new file mode 100644 index 0000000..2b7edcf --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/clock_power_pkg.vhd @@ -0,0 +1,31 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee; use ieee.std_logic_1164.all; +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +package clock_power_pkg is + + constant Tpw : delay_length := 4 ns; + + signal clock_phase1, clock_phase2 : std_ulogic; + + terminal analog_plus_supply, analog_ground : electrical; + +end package clock_power_pkg; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/packages/cpu-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/cpu-1.vhd new file mode 100644 index 0000000..e2fbe12 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/cpu-1.vhd @@ -0,0 +1,56 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- not in book + +entity cpu is +end entity cpu; + +-- end not in book + + + + +architecture behavioral of cpu is +begin + + interpreter : process is + + use work.cpu_types.all; + + variable instr_reg : word; + variable instr_opcode : opcode; + + begin + -- . . . -- initialize + loop + -- . . . -- fetch instruction + instr_opcode := extract_opcode ( instr_reg ); + case instr_opcode is + when op_nop => null; + when op_breq => -- . . . + -- . . . + -- not in book + when others => null; + -- end not in book + end case; + end loop; + end process interpreter; + +end architecture behavioral; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/packages/cpu.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/cpu.vhd new file mode 100644 index 0000000..c961c88 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/cpu.vhd @@ -0,0 +1,54 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- not in book + +entity cpu is +end entity cpu; + +-- end not in book + + + + +architecture behavioral of cpu is +begin + + interpreter : process is + + variable instr_reg : work.cpu_types.word; + variable instr_opcode : work.cpu_types.opcode; + + begin + -- . . . -- initialize + loop + -- . . . -- fetch instruction + instr_opcode := work.cpu_types.extract_opcode ( instr_reg ); + case instr_opcode is + when work.cpu_types.op_nop => null; + when work.cpu_types.op_breq => -- . . . + -- . . . + -- not in book + when others => null; + -- end not in book + end case; + end loop; + end process interpreter; + +end architecture behavioral; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/packages/cpu_types-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/cpu_types-1.vhd new file mode 100644 index 0000000..bf0bebd --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/cpu_types-1.vhd @@ -0,0 +1,56 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +package cpu_types is + + constant word_size : positive := 16; + constant address_size : positive := 24; + + subtype word is bit_vector(word_size - 1 downto 0); + subtype address is bit_vector(address_size - 1 downto 0); + + type status_value is ( halted, idle, fetch, mem_read, mem_write, + io_read, io_write, int_ack ); + + subtype opcode is bit_vector(5 downto 0); + + function extract_opcode ( instr_word : word ) return opcode; + + constant op_nop : opcode := "000000"; + constant op_breq : opcode := "000001"; + constant op_brne : opcode := "000010"; + constant op_add : opcode := "000011"; + -- . . . + +end package cpu_types; + + + +-- not in book + +package body cpu_types is + + function extract_opcode ( instr_word : word ) return opcode is + begin + return work.cpu_types.op_nop; + end function extract_opcode; + +end package body cpu_types; + +-- end not in book diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/packages/cpu_types.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/cpu_types.vhd new file mode 100644 index 0000000..10d497c --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/cpu_types.vhd @@ -0,0 +1,51 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- code from book + +package cpu_types is + + constant word_size : positive := 16; + constant address_size : positive := 24; + + subtype word is bit_vector(word_size - 1 downto 0); + subtype address is bit_vector(address_size - 1 downto 0); + + type status_value is ( halted, idle, fetch, mem_read, mem_write, + io_read, io_write, int_ack ); + +end package cpu_types; + +-- end code from book + + + +package cpu_types_test is + + constant status : + -- code from book + work.cpu_types.status_value + -- end code from book + := + -- code from book + work.cpu_types.status_value'(work.cpu_types.fetch) + -- end code from book + ; + +end package cpu_types_test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/packages/index-ams.txt b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/index-ams.txt new file mode 100644 index 0000000..4e8165c --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/index-ams.txt @@ -0,0 +1,39 @@ +--------------------------------------------------------------------------------------------------------------------------------------------- +-- Chapter 10 - Packages +--------------------------------------------------------------------------------------------------------------------------------------------- +-- Filename Primary Unit Secondary Unit Figure/Section +----------- ------------ -------------- -------------- +cpu_types.vhd package cpu_types -- Figure 10-1 +-- package cpu_types_test -- Section 10.1 +address_decoder.vhd entity address_decoder functional Figure 10-2 +clock_power_pkg.vhd package clock_power_pkg -- Figure 10-3 +io_controller-1.vhd entity phase_locked_clock_gen std_cell -- +-- entity regulator device_level -- +-- entity io_controller top_level Figure 10-4 +bus_sequencer-1.vhd entity state_register std_cell -- +-- entity bus_sequencer fsm Figure 10-5 +analog_output_interface.vhd entity analog_interface_dac macroblock -- +-- entity analog_output_interface structural Figure 10-6 +cpu_types-1.vhd package cpu_types -- Figure 10-7 +cpu.vhd entity cpu behavioral Figure 10-8 +bit_vector_signed_arithmetic.vhd package bit_vector_signed_arithmetic body Figure 10-9 +cpu-1.vhd entity cpu behavioral Figure 10-10 +lessthan.vhd entity lessthan test Figure 10-11 +test_alu.vhd package alu_types -- Section 10.5 +-- entity ALU structural Section 10.5 +-- test_alu random_test Figure 10-14 +inline_01.vhd entity inline_01 test Section 10.1 +inline_02.vhd package inline_02 body Section 10.1 +inline_03.vhd entity inline_03 test Section 10.3 +inline_04a.vhd entity inline_04a test Section 10.3 +inline_05.vhd entity logic_block -- Section 10.3 +inline_06.vhd entity inline_06 test Section 10.4 +inline_08.vhd package inline_08 -- Section 10.5 +inline_09.vhd entity inline_09 test Section 10.5 +--------------------------------------------------------------------------------------------------------------------------------------------- +-- TestBenches +--------------------------------------------------------------------------------------------------------------------------------------------- +-- Filename Primary Unit Secondary Unit Tested Model +------------ ------------ -------------- ------------ +tb_address_decoder.vhd entity tb_address_decoder test address_decoder.vhd +tb_bit_vector_signed_arithmetic.vhd tb_bit_vector_signed_arithmetic test bit_vector_signed_arithmetic.vhd diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_01.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_01.vhd new file mode 100644 index 0000000..641ba6b --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_01.vhd @@ -0,0 +1,45 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity inline_01 is + +end entity inline_01; + + +library ieee; + +architecture test of inline_01 is + +begin + + process_1_a : process is + + -- code from book: + + variable stored_state : ieee.std_logic_1164.std_ulogic; + + -- end of code from book + + begin + + wait; + end process process_1_a; + + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_02.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_02.vhd new file mode 100644 index 0000000..0019d2e --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_02.vhd @@ -0,0 +1,46 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +package inline_02 is + + -- code from book + + subtype word32 is bit_vector(31 downto 0); + + procedure add ( a, b : in word32; + result : out word32; overflow : out boolean ); + + function "<" ( a, b : in word32 ) return boolean; + + constant max_buffer_size : positive; + + -- end code from book + +end package inline_02; + + +package body inline_02 is + + -- code from book + + constant max_buffer_size : positive := 4096; + + -- end code from book + +end package body inline_02; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_03.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_03.vhd new file mode 100644 index 0000000..640c35e --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_03.vhd @@ -0,0 +1,69 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity inline_03 is + +end entity inline_03; + + +---------------------------------------------------------------- + + +library ieee; + +architecture test of inline_03 is +begin + + + process_3_a : process is + + -- code from book: + + use work.cpu_types; + + variable data_word : cpu_types.word; + variable next_address : cpu_types.address; + + -- end of code from book + + begin + wait; + end process process_3_a; + + + ---------------- + + + process_3_b : process is + + -- code from book: + + use work.cpu_types.word, work.cpu_types.address; + + variable data_word : word; + variable next_address : address; + + -- end of code from book + + begin + wait; + end process process_3_b; + + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_04a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_04a.vhd new file mode 100644 index 0000000..6d695d0 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_04a.vhd @@ -0,0 +1,46 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity inline_04a is + +end entity inline_04a; + + +---------------------------------------------------------------- + + +library ieee_proposed; + +architecture test of inline_04a is +begin + + + block_3_c : block is + + -- code from book: + + use ieee_proposed.electrical_systems.all; + + -- end of code from book + + begin + end block block_3_c; + + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_05.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_05.vhd new file mode 100644 index 0000000..c8b9f9e --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_05.vhd @@ -0,0 +1,25 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee; use ieee.std_logic_1164.std_ulogic; + +entity logic_block is + port ( a, b : in std_ulogic; + y, z : out std_ulogic ); +end entity logic_block; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_06.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_06.vhd new file mode 100644 index 0000000..c6e2f6e --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_06.vhd @@ -0,0 +1,57 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- code from book: + +library std, work; use std.standard.all; + +-- end of code from book + + +entity inline_06 is + +end entity inline_06; + + +---------------------------------------------------------------- + + +architecture test of inline_06 is +begin + + + process_4_a : process is + + constant a : integer := 10; + constant b : integer := 20; + variable result : boolean; + + begin + + -- code from book: + + result := std.standard."<" ( a, b ); + + -- end of code from book + + wait; + end process process_4_a; + + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_08.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_08.vhd new file mode 100644 index 0000000..9c6bdf4 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_08.vhd @@ -0,0 +1,29 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +package inline_08 is + + -- code from book + + procedure uniform ( variable seed1, seed2 : inout positive; + variable x : out real); + + -- end code from book + +end package inline_08; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_09.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_09.vhd new file mode 100644 index 0000000..c26ede7 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_09.vhd @@ -0,0 +1,59 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee; + +entity inline_09 is + +end entity inline_09; + + +---------------------------------------------------------------- + + +architecture test of inline_09 is +begin + + process_5_c : process is + + use ieee.math_real.all; + + -- code from book + + type complex is record + re : real; -- Real part + im : real; -- Imaginary part + end record; + + subtype positive_real is real range 0.0 to real'high; + subtype principal_value is real range -math_pi to math_pi; + + type complex_polar is record + mag : positive_real; -- Magnitude + arg : principal_value; -- Angle in radians; -math_pi is illegal + end record; + + -- end of code from book + + begin + wait; + end process process_5_c; + + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/packages/io_controller-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/io_controller-1.vhd new file mode 100644 index 0000000..56fb1fa --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/io_controller-1.vhd @@ -0,0 +1,116 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- not in book + +library ieee; use ieee.std_logic_1164.all; + +entity phase_locked_clock_gen is + port ( ref_clock : in std_ulogic; + phi1, phi2 : out std_ulogic ); +end entity phase_locked_clock_gen; + + +architecture std_cell of phase_locked_clock_gen is + + use work.clock_power_pkg.Tpw; + +begin + + phi1_gen : phi1 <= '1', '0' after Tpw when rising_edge(ref_clock); + + phi2_gen : phi2 <= '1', '0' after Tpw when falling_edge(ref_clock); + +end architecture std_cell; + + +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity regulator is + port ( terminal plus_in, minus_in, plus_out, minus_out : electrical ); +end entity regulator; + + +architecture device_level of regulator is +begin +end architecture device_level; + + + + +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +-- end not in book + + + +library ieee; use ieee.std_logic_1164.all; + +entity io_controller is + port ( signal ref_clock : in std_ulogic; + terminal ext_supply, ext_ground : electrical; -- . . . ); + -- not in book + other_port : in std_ulogic ); + -- end not in book +end entity io_controller; + +-------------------------------------------------- + +architecture top_level of io_controller is + + -- . . . + + -- not in book + signal rd, wr, sel, width, burst : std_ulogic; + signal addr : std_ulogic_vector(3 downto 0); + signal ready : std_ulogic; + signal control_reg_wr, status_reg_rd, data_fifo_wr, data_fifo_rd, + other_signal : std_ulogic; + + signal analog_out_wr_0 : std_ulogic; + signal internal_data : std_ulogic_vector(7 downto 0); + terminal analog_out_0 : electrical; + -- end not in book + +begin + + internal_clock_gen : entity work.phase_locked_clock_gen(std_cell) + port map ( ref_clock => ref_clock, + phi1 => work.clock_power_pkg.clock_phase1, + phi2 => work.clock_power_pkg.clock_phase2 ); + + internal_analog_regulator : entity work.regulator(device_level) + port map ( plus_in => ext_supply, minus_in => ext_ground, + plus_out => work.clock_power_pkg.analog_plus_supply, + minus_out => work.clock_power_pkg.analog_ground ); + + the_bus_sequencer : entity work.bus_sequencer(fsm) + port map ( rd, wr, sel, width, burst, addr(3 downto 0), ready, + control_reg_wr, status_reg_rd, data_fifo_wr, data_fifo_rd, + analog_out_wr_0, -- . . . ); + -- not in book + other_signal ); + -- not in book + + analog_output_interface_0 : entity work.analog_output_interface(structural) + port map ( analog_out_wr_0, internal_data(7 downto 0), analog_out_0 ); + + -- . . . + +end architecture top_level; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/packages/lessthan.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/lessthan.vhd new file mode 100644 index 0000000..4a97200 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/lessthan.vhd @@ -0,0 +1,61 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity lessthan is +end entity lessthan; + + + +architecture test of lessthan is + + -- code from book + + function "<" ( a, b : bit_vector ) return boolean is + variable tmp1 : bit_vector(a'range) := a; + variable tmp2 : bit_vector(b'range) := b; + begin + tmp1(tmp1'left) := not tmp1(tmp1'left); + tmp2(tmp2'left) := not tmp2(tmp2'left); + return std.standard."<" ( tmp1, tmp2 ); + end function "<"; + + -- end code from book + + signal a, b : bit_vector(7 downto 0); + signal result : boolean; + +begin + + dut : result <= a < b; + + stimulus : process is + begin + wait for 10 ns; + a <= X"02"; b <= X"04"; wait for 10 ns; + a <= X"02"; b <= X"02"; wait for 10 ns; + a <= X"02"; b <= X"01"; wait for 10 ns; + a <= X"02"; b <= X"FE"; wait for 10 ns; + a <= X"FE"; b <= X"02"; wait for 10 ns; + a <= X"FE"; b <= X"FE"; wait for 10 ns; + a <= X"FE"; b <= X"FC"; wait for 10 ns; + + wait; + end process stimulus; + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/packages/tb_address_decoder.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/tb_address_decoder.vhd new file mode 100644 index 0000000..7be5b79 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/tb_address_decoder.vhd @@ -0,0 +1,80 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity tb_address_decoder is +end entity tb_address_decoder; + + +architecture test of tb_address_decoder is + + use work.cpu_types.all; + + signal addr : address := X"000000"; + signal status : status_value := idle; + signal mem_sel, int_sel, io_sel : bit; + +begin + + dut : entity work.address_decoder + port map ( addr => addr, status => status, + mem_sel => mem_sel, int_sel => int_sel, io_sel => io_sel ); + + stimulus : process is + begin + wait for 10 ns; + + status <= fetch; wait for 10 ns; + status <= mem_read; wait for 10 ns; + status <= mem_write; wait for 10 ns; + status <= io_read; wait for 10 ns; + status <= io_write; wait for 10 ns; + status <= int_ack; wait for 10 ns; + status <= idle; wait for 10 ns; + + addr <= X"EFFFFF"; wait for 10 ns; + status <= fetch; wait for 10 ns; + status <= mem_read; wait for 10 ns; + status <= mem_write; wait for 10 ns; + status <= io_read; wait for 10 ns; + status <= io_write; wait for 10 ns; + status <= int_ack; wait for 10 ns; + status <= idle; wait for 10 ns; + + addr <= X"F00000"; wait for 10 ns; + status <= fetch; wait for 10 ns; + status <= mem_read; wait for 10 ns; + status <= mem_write; wait for 10 ns; + status <= io_read; wait for 10 ns; + status <= io_write; wait for 10 ns; + status <= int_ack; wait for 10 ns; + status <= idle; wait for 10 ns; + + addr <= X"FFFFFF"; wait for 10 ns; + status <= fetch; wait for 10 ns; + status <= mem_read; wait for 10 ns; + status <= mem_write; wait for 10 ns; + status <= io_read; wait for 10 ns; + status <= io_write; wait for 10 ns; + status <= int_ack; wait for 10 ns; + status <= idle; wait for 10 ns; + + wait; + end process stimulus; + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/packages/tb_bit_vector_signed_arithmetic.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/tb_bit_vector_signed_arithmetic.vhd new file mode 100644 index 0000000..130f1dc --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/tb_bit_vector_signed_arithmetic.vhd @@ -0,0 +1,48 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity tb_bit_vector_signed_arithmetic is +end entity tb_bit_vector_signed_arithmetic; + + +architecture test of tb_bit_vector_signed_arithmetic is +begin + + stimulus : process is + use work.bit_vector_signed_arithmetic.all; + use std.textio.all; + variable L : line; + begin + write(L, X"0002" + X"0005"); + writeline(output, L); + write(L, X"0002" + X"FFFE"); + writeline(output, L); + write(L, - X"0005"); + writeline(output, L); + write(L, - X"FFFE"); + writeline(output, L); + write(L, X"0002" * X"0005"); + writeline(output, L); + write(L, X"0002" * X"FFFD"); + writeline(output, L); + + wait; + end process stimulus; + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/packages/test_alu.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/test_alu.vhd new file mode 100644 index 0000000..3ed4d1a --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/test_alu.vhd @@ -0,0 +1,101 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee; + +package alu_types is + + -- code from book (in text) + + use ieee.numeric_bit.all; + subtype ALU_func is unsigned(3 downto 0); + subtype data_word is unsigned(15 downto 0); + -- . . . + + -- end code from book (in text) + +end package alu_types; + + + +use work.alu_types.all; + +-- code from book (in text) + +entity ALU is + port ( a, b : in data_word; func : in ALU_func; + result : out data_word; carry : out bit ); +end entity ALU; + +-- end code from book (in text) + + + +architecture structural of ALU is +begin +end architecture structural; + + +entity test_ALU is +end entity test_ALU; + + + +library ieee; +use work.alu_types.all; + +-- code from book + +architecture random_test of test_ALU is + + use ieee.numeric_bit.all; + use ieee.math_real.uniform; + + signal a, b, result : data_word; + signal func : ALU_func; + signal carry : bit; + +begin + + dut : entity work.ALU(structural) + port map ( a, b, func, result, carry ); + + stimulus : process is + variable seed1, seed2 : positive := 1; + variable a_real, b_real, func_real : real; + begin + wait for 100 ns; + uniform ( seed1, seed2, a_real ); + uniform ( seed1, seed2, b_real ); + uniform ( seed1, seed2, func_real ); + a <= to_unsigned( natural(a_real * real(2**integer'(data_word'length)) - 0.5), + data_word'length ); + b <= to_unsigned( natural(b_real * real(2**integer'(data_word'length)) - 0.5), + data_word'length ); + func <= to_unsigned( natural(func_real + * real(2**integer'(ALU_func'length)) - 0.5), + ALU_func'length ); + end process stimulus; + + -- . . . --verification process to check result and carry + +end architecture random_test; + +-- end code from book + |