1 files changed, 56 insertions, 0 deletions
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/packages/cpu-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/cpu-1.vhd
new file mode 100644
index 0000000..e2fbe12
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+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/cpu-1.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- not in book
+
+entity cpu is
+end entity cpu;
+
+-- end not in book
+
+
+
+
+architecture behavioral of cpu is
+begin
+
+  interpreter : process is
+
+    use work.cpu_types.all;
+
+    variable instr_reg : word;
+    variable instr_opcode : opcode;
+
+  begin
+    -- . . .    -- initialize
+    loop
+      -- . . .    -- fetch instruction
+      instr_opcode := extract_opcode ( instr_reg );
+      case instr_opcode is
+        when op_nop => null;
+        when op_breq => -- . . .
+        -- . . .
+        -- not in book
+        when others => null;
+        -- end not in book
+      end case;
+    end loop;
+  end process interpreter;
+
+end architecture behavioral;