diff options
Diffstat (limited to 'testsuite/vests/vhdl-ams/ashenden/compliant/composite-data')
27 files changed, 1888 insertions, 0 deletions
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/and_multiple.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/and_multiple.vhd new file mode 100644 index 0000000..5982329 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/and_multiple.vhd @@ -0,0 +1,39 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity and_multiple is + port ( i : in bit_vector; y : out bit ); +end entity and_multiple; + +-------------------------------------------------- + +architecture behavioral of and_multiple is +begin + + and_reducer : process ( i ) is + variable result : bit; + begin + result := '1'; + for index in i'range loop + result := result and i(index); + end loop; + y <= result; + end process and_reducer; + +end architecture behavioral; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/byte_swap.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/byte_swap.vhd new file mode 100644 index 0000000..105f11f --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/byte_swap.vhd @@ -0,0 +1,50 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- not in book: + +package byte_swap_types is + + subtype halfword is bit_vector(0 to 15); + +end package byte_swap_types; + + +use work.byte_swap_types.all; + +-- end not in book: + + +entity byte_swap is + port (input : in halfword; output : out halfword); +end entity byte_swap; + +-------------------------------------------------- + +architecture behavior of byte_swap is + +begin + + swap : process (input) + begin + output(8 to 15) <= input(0 to 7); + output(0 to 7) <= input(8 to 15); + end process swap; + +end architecture behavior; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/coeff_ram.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/coeff_ram.vhd new file mode 100644 index 0000000..8650058 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/coeff_ram.vhd @@ -0,0 +1,63 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- not in book: + +package coeff_ram_types is + + subtype coeff_ram_address is integer range 0 to 63; + +end package coeff_ram_types; + + + +use work.coeff_ram_types.all; + +-- end not in book + + +entity coeff_ram is + port ( rd, wr : in bit; addr : in coeff_ram_address; + d_in : in real; d_out : out real ); +end entity coeff_ram; + +-------------------------------------------------- + +architecture abstract of coeff_ram is +begin + + memory : process is + type coeff_array is array (coeff_ram_address) of real; + variable coeff : coeff_array; + begin + for index in coeff_ram_address loop + coeff(index) := 0.0; + end loop; + loop + wait on rd, wr, addr, d_in; + if rd = '1' then + d_out <= coeff(addr); + end if; + if wr = '1' then + coeff(addr) := d_in; + end if; + end loop; + end process memory; + +end architecture abstract; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/computer.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/computer.vhd new file mode 100644 index 0000000..2fd0f47 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/computer.vhd @@ -0,0 +1,101 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- not in book: + +entity computer is + +end entity computer; + +-- end not in book + + +architecture system_level of computer is + + type opcodes is (add, sub, addu, subu, jmp, breq, brne, ld, st, -- . . .); + -- not in book: + nop); + -- end not in book + type reg_number is range 0 to 31; + constant r0 : reg_number := 0; constant r1 : reg_number := 1; -- . . . + -- not in book: + constant r2 : reg_number := 2; + -- end not in book + + type instruction is record + opcode : opcodes; + source_reg1, source_reg2, dest_reg : reg_number; + displacement : integer; + end record instruction; + + type word is record + instr : instruction; + data : bit_vector(31 downto 0); + end record word; + + signal address : natural; + signal read_word, write_word : word; + signal mem_read, mem_write : bit := '0'; + signal mem_ready : bit := '0'; + +begin + + cpu : process is + variable instr_reg : instruction; + variable PC : natural; + -- . . . -- other declarations for register file, etc. + begin + address <= PC; + mem_read <= '1'; + wait until mem_ready = '1'; + instr_reg := read_word.instr; + mem_read <= '0'; + -- not in book: + wait until mem_ready = '0'; + -- end not in book + PC := PC + 4; + case instr_reg.opcode is -- execute the instruction + -- . . . + -- not in book: + when others => null; + -- end not in book + end case; + end process cpu; + + memory : process is + subtype address_range is natural range 0 to 2**14 - 1; + type memory_array is array (address_range) of word; + variable store : memory_array := + ( 0 => ( ( ld, r0, r0, r2, 40 ), X"00000000" ), + 1 => ( ( breq, r2, r0, r0, 5 ), X"00000000" ), + -- . . . + 40 => ( ( nop, r0, r0, r0, 0 ), X"FFFFFFFE"), + others => ( ( nop, r0, r0, r0, 0 ), X"00000000") ); + begin + -- . . . + -- not in book: + wait until mem_read = '1'; + read_word <= store(address); + mem_ready <= '1'; + wait until mem_read = '0'; + mem_ready <= '0'; + -- end not in book + end process memory; + +end architecture system_level; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/index-ams.txt b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/index-ams.txt new file mode 100644 index 0000000..9bcec81 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/index-ams.txt @@ -0,0 +1,39 @@ +--------------------------------------------------------------------------------------------------------------------------------------------- +-- Chapter 4 - Composite Data Types +--------------------------------------------------------------------------------------------------------------------------------------------- +-- Filename Primary Unit Secondary Unit Figure/Section +----------- ------------ -------------- -------------- +coeff_ram.vhd package coeff_ram_types -- Section 4.1 +-- entity coeff_ram abstract Figure 4-1 +transmission_lines.vhd package transmission_lines_types -- Section 4.1 +-- entity transmission_lines abstract Figure 4-2 +modem_controller.vhd entity modem_controller test Figure 4-4 +and_multiple.vhd entity and_multiple behavioral Figure 4-5 +tb_and_multiple.vhd tb_and_multiple test_behavioral Section 4.2 +byte_swap.vhd package byte_swap_types -- Section 4.3 +-- entity byte_swap behavior Figure 4-6 +computer.vhd entity computer system_level Figure 4-7 +inline_01.vhd entity inline_01 test Section 4.1 +inline_02a.vhd entity inline_02a test Section 4.1 +inline_03.vhd entity inline_03 test Section 4.1 +inline_04a.vhd entity inline_04a test Section 4.1 +inline_05.vhd entity inline_05 test Section 4.1 +inline_06a.vhd entity inline_06a test Section 4.1 +inline_07a.vhd entity inline_07a test Section 4.1 +inline_08.vhd entity inline_08 test Section 4.2 +inline_09a.vhd entity inline_09a test Section 4.2 +inline_10.vhd entity inline_10 test Section 4.2 +inline_11a.vhd entity inline_11a test Section 4.2 +inline_12.vhd entity inline_12 test Section 4.3 +inline_13.vhd entity inline_13 test Section 4.3 +inline_14a.vhd entity inline_14a test Section 4.3 +inline_15.vhd entity inline_15 test Section 4.3 +inline_16.vhd entity inline_16 test Section 4.4 +inline_17a.vhd entity inline_17a test Section 4.4 +--------------------------------------------------------------------------------------------------------------------------------------------- +-- TestBenches +--------------------------------------------------------------------------------------------------------------------------------------------- +-- Filename Primary Unit Secondary Unit Tested Model +------------ ------------ -------------- ------------ +tb_coeff_ram.vhd entity tb_coeff_ram test_abstract coeff_ram.vhd +tb_byte_swap.vhd entity tb_byte_swap test_behavior byte_swap.vhd diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_01.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_01.vhd new file mode 100644 index 0000000..4997a79 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_01.vhd @@ -0,0 +1,94 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity inline_01 is + +end entity inline_01; + + +---------------------------------------------------------------- + + +architecture test of inline_01 is +begin + + + block_1_a : block is + + -- code from book: + + type word is array (0 to 31) of bit; + + -- + + type controller_state is (initial, idle, active, error); + + type state_counts is array (idle to error) of natural; + + -- end of code from book + + begin + end block block_1_a; + + + process_1_a : process is + + -- code from book: + + type word is array (31 downto 0) of bit; + + -- + + type controller_state is (initial, idle, active, error); + + -- + + type state_counts is + array (controller_state range idle to error) of natural; + + -- + + subtype coeff_ram_address is integer range 0 to 63; + type coeff_array is array (coeff_ram_address) of real; + + -- + + variable buffer_register, data_register : word; + variable counters : state_counts; + variable coeff : coeff_array; + + -- end of code from book + + begin + + -- code from book: + + coeff(0) := 0.0; + + counters(active) := counters(active) + 1; + + data_register := buffer_register; + + -- end of code from book + + wait; + end process process_1_a; + + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_02a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_02a.vhd new file mode 100644 index 0000000..cac5cfb --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_02a.vhd @@ -0,0 +1,99 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee_proposed; use ieee_proposed.electrical_systems.all; +use ieee_proposed.fluidic_systems.all; + +entity inline_02a is + +end entity inline_02a; + + +---------------------------------------------------------------- + + +architecture test of inline_02a is +begin + + + block_1_a : block is + + -- code from book: + + nature electrical_bus is array (0 to 31) of electrical; + + -- end of code from book + + begin + end block block_1_a; + + + block_1_b : block is + + -- code from book: + + nature electrical_bus is array (31 downto 0) of electrical; + + -- end of code from book + + begin + end block block_1_b; + + + block_1_c : block is + + -- code from book: + + type engine_nodes is (intake, compressor, combustion, exhaust); + + -- + + nature engine_flows is array (intake to exhaust) of fluidic; + + -- + + subtype bus_lines is integer range 0 to 31; + nature electrical_bus is array (bus_lines) of electrical; + + -- + + subtype pressure is real tolerance "default_pressure"; + subtype pipes is integer range 0 to 15; + + -- + + type gas_pressures is array (pipes) of pressure; + + -- + + terminal system_bus : electrical_bus; + terminal ferrari_engine, chevy_engine : engine_flows; + + -- + + quantity bus_voltages across bus_currents through + system_bus to electrical_ref; + + -- end of code from book + + begin + end block block_1_c; + + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_03.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_03.vhd new file mode 100644 index 0000000..5414554 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_03.vhd @@ -0,0 +1,92 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity inline_03 is + +end entity inline_03; + + +---------------------------------------------------------------- + + +architecture test of inline_03 is +begin + + + process_1_b : process is + + -- code from book: + + type symbol is ('a', 't', 'd', 'h', digit, cr, error); + type state is range 0 to 6; + + type transition_matrix is array (state, symbol) of state; + + variable transition_table : transition_matrix; + + -- end of code from book + + variable next_state : state; + + -- code from book: + + type point is array (1 to 3) of real; + type matrix is array (1 to 3, 1 to 3) of real; + + variable p, q : point; + variable transform : matrix; + + -- end of code from book + + begin + + next_state := + -- code from book: + + transition_table(5, 'd'); + + + -- end of code from book + + for i in 1 to 3 loop + for j in 1 to 3 loop + if i = j then + transform(i, j) := -1.0; + else + transform(i, j) := 0.0; + end if; + end loop; + end loop; + p := (1.0, 2.0, 3.0); + + -- code from book: + + for i in 1 to 3 loop + q(i) := 0.0; + for j in 1 to 3 loop + q(i) := q(i) + transform(i, j) * p(j); + end loop; + end loop; + -- end of code from book + + wait; + end process process_1_b; + + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_04a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_04a.vhd new file mode 100644 index 0000000..6b44e1d --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_04a.vhd @@ -0,0 +1,76 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee_proposed; use ieee_proposed.mechanical_systems.all; +use ieee_proposed.fluidic_systems.all; + +entity inline_04a is + +end entity inline_04a; + + +---------------------------------------------------------------- + + +architecture test of inline_04a is + + -- code from book: + + type engine_nodes is (intake, compressor, combustion, exhaust); + type engines is range 1 to 4; + nature aircraft_engine_flows is array (engine_nodes, engines) of fluidic; + + -- + + nature sensor_matrix is array (1 to 100, 1 to 100) of translational; + + -- + + terminal sensor_grid : sensor_matrix; + + -- + + quantity sensor_data across sensor_grid to translational_ref; + + -- end of code from book + +begin + + + process_1_b : process is + variable total_displacement, average_displacement : real; + begin + + -- code from book: + + total_displacement := 0.0; + for x in 1 to 100 loop + for y in 1 to 100 loop + total_displacement := total_displacement + sensor_data(x, y); + end loop; + end loop; + average_displacement := total_displacement / 10000.0; + + --end code from book + + wait; + end process process_1_b; + + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_05.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_05.vhd new file mode 100644 index 0000000..c3e1239 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_05.vhd @@ -0,0 +1,125 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity inline_05 is + +end entity inline_05; + + +---------------------------------------------------------------- + + +architecture test of inline_05 is + + subtype coeff_ram_address is integer range 0 to 63; + + -- code from book: + + type coeff_array is array (coeff_ram_address) of real; + + -- end of code from book + + +begin + + + process_1_c : process is + + -- code from book: + + type point is array (1 to 3) of real; + constant origin : point := (0.0, 0.0, 0.0); + variable view_point : point := (10.0, 20.0, 0.0); + + -- end of code from book + + begin + wait; + end process process_1_c; + + + process_1_d : process is + + type point is array (1 to 3) of real; + + -- code from book: + + variable view_point : point := (1 => 10.0, 2 => 20.0, 3 => 0.0); + + -- end of code from book + + begin + wait; + end process process_1_d; + + + process_1_e : process is + + -- code from book: + + variable coeff : coeff_array := (0 => 1.6, 1 => 2.3, 2 => 1.6, 3 to 63 => 0.0); + + -- end of code from book + + begin + wait; + end process process_1_e; + + + process_1_f : process is + + -- code from book: + + variable coeff : coeff_array := (0 => 1.6, 1 => 2.3, 2 => 1.6, others => 0.0); + + -- end of code from book + + begin + wait; + end process process_1_f; + + + process_1_g : process is + + -- code from book: + + variable coeff : coeff_array := (0 | 2 => 1.6, 1 => 2.3, others => 0.0); + + -- end of code from book + + begin + wait; + end process process_1_g; + + + process_1_h : process is + + -- code from book: + + -- error: Associations in array aggregate must be all named or all positional + -- variable coeff : coeff_array := (1.6, 2.3, 2 => 1.6, others => 0.0); -- illegal + + -- end of code from book + + begin + wait; + end process process_1_h; + + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_06a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_06a.vhd new file mode 100644 index 0000000..317ea13 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_06a.vhd @@ -0,0 +1,54 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity inline_06a is + +end entity inline_06a; + + +---------------------------------------------------------------- + + +architecture test of inline_06a is + + -- code from book: + + subtype resistance is real tolerance "default_resistance"; + type resistance_array is array (1 to 4) of resistance; + quantity resistances : resistance_array := (10.0, 20.0, 50.0, 75.0); + + -- end of code from book + + +begin + + + block_1_f : block is + + -- code from book: + + quantity resistances : resistance_array := (1 => 10.0, 2 => 20.0, 3 => 50.0, 4 => 75.0); + + -- end of code from book + + begin + end block block_1_f; + + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_07a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_07a.vhd new file mode 100644 index 0000000..1a3daf3 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_07a.vhd @@ -0,0 +1,79 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity inline_07a is + +end entity inline_07a; + + +---------------------------------------------------------------- + + +library ieee_proposed; use ieee_proposed.thermal_systems.all; + +architecture test of inline_07a is + + -- code from book: + + type A is array (1 to 4, 31 downto 0) of boolean; + + nature B is array (1 to 10, 19 downto 0) of thermal; + + -- end of code from book + +begin + + + process_1_i : process is + + variable free_map : bit_vector(1 to 10) := "0011010110"; + variable count : natural; + + begin + + -- code from book (just the conditions): + + assert A'low(1) = 1; assert B'left(1) = 1; + assert A'high(2) = 31; assert B'right(2) = 0; + +-- assert A'reverse_range(2) is 0 to 31; assert B'range(1) is 1 to 10; + + assert A'length(2) = 32; assert B'length(1) = 10; + + assert A'ascending(2) = false; assert B'ascending(1) = true; + + assert A'low = 1; assert A'length = 4; + assert B'high = 10; assert B'length = 10; + + -- + + count := 0; + for index in free_map'range loop + if free_map(index) = '1' then + count := count + 1; + end if; + end loop; + + -- end of code from book + + wait; + end process process_1_i; + + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_08.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_08.vhd new file mode 100644 index 0000000..51d617f --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_08.vhd @@ -0,0 +1,54 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity inline_08 is + +end entity inline_08; + + +---------------------------------------------------------------- + + +architecture test of inline_08 is +begin + + + process_2_a : process is + + -- code from book: + + type sample is array (natural range <>) of integer; + + variable short_sample_buf : sample(0 to 63); + + subtype long_sample is sample(0 to 255); + variable new_sample_buf, old_sample_buf : long_sample; + + constant lookup_table : sample := ( 1 => 23, 3 => -16, 2 => 100, 4 => 11); + + constant beep_sample : sample := ( 127, 63, 0, -63, -127, -63, 0, 63 ); + + -- end of code from book + + begin + wait; + end process process_2_a; + + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_09a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_09a.vhd new file mode 100644 index 0000000..7b4c161 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_09a.vhd @@ -0,0 +1,44 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity inline_09a is + +end entity inline_09a; + + +---------------------------------------------------------------- + + +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +architecture test of inline_09a is + + -- code from book: + + nature electrical_vector is array (natural range <>) of electrical; + + terminal local_bus : electrical_vector(15 downto 0); + + subnature long_bus is electrical_vector(7 downto 0); + terminal remote_bus : long_bus; + + -- end of code from book + +begin +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_10.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_10.vhd new file mode 100644 index 0000000..b5dc185 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_10.vhd @@ -0,0 +1,99 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity inline_10 is + +end entity inline_10; + + +---------------------------------------------------------------- + + +library ieee; use ieee.std_logic_1164.std_ulogic; + +architecture test of inline_10 is + + -- code from book: + + type std_ulogic_vector is array ( natural range <> ) of std_ulogic; + + -- + + subtype std_ulogic_word is std_ulogic_vector(0 to 31); + + -- + + signal csr_offset : std_ulogic_vector(2 downto 1); + + -- end of code from book + +begin + + + process_2_b : process is + + -- code from book: + + type string is array (positive range <>) of character; + + -- + + constant LCD_display_len : positive := 20; + subtype LCD_display_string is string(1 to LCD_display_len); + variable LCD_display : LCD_display_string := (others => ' '); + + -- + + type bit_vector is array (natural range <>) of bit; + + -- + + subtype byte is bit_vector(7 downto 0); + + -- + + variable channel_busy_register : bit_vector(1 to 4); + + -- + + constant ready_message : string := "Ready "; + + -- + + variable current_test : std_ulogic_vector(0 to 13) := "ZZZZZZZZZZ----"; + + -- + + constant all_ones : std_ulogic_vector(15 downto 0) := X"FFFF"; + + -- end of code from book + + begin + + -- code from book: + + channel_busy_register := b"0000"; + + -- end of code from book + + wait; + end process process_2_b; + + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_11a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_11a.vhd new file mode 100644 index 0000000..1ba0a34 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_11a.vhd @@ -0,0 +1,45 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity inline_11a is + +end entity inline_11a; + + +---------------------------------------------------------------- + + +architecture test of inline_11a is + + -- code from book: + + type real_vector is array (natural range <>) of real; + + -- + + subtype gains is real_vector(15 downto 0); + + -- + + quantity max_temperatures : real_vector(1 to 10); + + -- end of code from book + +begin +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_12.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_12.vhd new file mode 100644 index 0000000..84c242f --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_12.vhd @@ -0,0 +1,82 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity inline_12 is + +end entity inline_12; + + +---------------------------------------------------------------- + + +architecture test of inline_12 is +begin + + + process_3_a : process is + + -- code from book: + + subtype pixel_row is bit_vector (0 to 15); + variable current_row, mask : pixel_row; + + -- end of code from book + + begin + + current_row := "0000000011111111"; + mask := "0000111111110000"; + + -- code from book: + + current_row := current_row and not mask; + current_row := current_row xor X"FFFF"; + + -- end of code from book + + -- code from book (conditions only): + + assert B"10001010" sll 3 = B"01010000"; + assert B"10001010" sll -2 = B"00100010"; + + assert B"10010111" srl 2 = B"00100101"; + assert B"10010111" srl -6 = B"11000000"; + + assert B"01001011" sra 3 = B"00001001"; + assert B"10010111" sra 3 = B"11110010"; + assert B"00001100" sla 2 = B"00110000"; + assert B"00010001" sla 2 = B"01000111"; + + assert B"00010001" sra -2 = B"01000111"; + assert B"00110000" sla -2 = B"00001100"; + + assert B"10010011" rol 1 = B"00100111"; + assert B"10010011" ror 1 = B"11001001"; + + assert "abc" & 'd' = "abcd"; + assert 'w' & "xyz" = "wxyz"; + assert 'a' & 'b' = "ab"; + + -- end of code from book + + wait; + end process process_3_a; + + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_13.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_13.vhd new file mode 100644 index 0000000..9eef5af --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_13.vhd @@ -0,0 +1,59 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity inline_13 is + +end entity inline_13; + + +---------------------------------------------------------------- + + +architecture test of inline_13 is +begin + + + process_3_b : process is + + -- code from book: + + type array1 is array (1 to 100) of integer; + type array2 is array (100 downto 1) of integer; + + variable a1 : array1; + variable a2 : array2; + + -- end of code from book + + begin + + a1(11 to 20) := a1(11 to 20); + a2(50 downto 41) := a2(50 downto 41); + + a1(10 to 1) := a1(10 to 1); + a2(1 downto 10) := a2(1 downto 10); + + a1(10 downto 1) := a1(10 downto 1); -- illegal + a2(1 to 10) := a2(1 to 10); -- illegal; + + wait; + end process process_3_b; + + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_14a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_14a.vhd new file mode 100644 index 0000000..ab0fa8b --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_14a.vhd @@ -0,0 +1,39 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity inline_14a is + +end entity inline_14a; + + +---------------------------------------------------------------- + + +architecture test of inline_14a is + + -- code from book: + + type array3 is array (10 downto 1) of real tolerance "default"; + + quantity a3 : array3; + + -- end of code from book + +begin +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_15.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_15.vhd new file mode 100644 index 0000000..cd58766 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_15.vhd @@ -0,0 +1,79 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity inline_15 is + +end entity inline_15; + + +---------------------------------------------------------------- + + +architecture test of inline_15 is +begin + + + process_3_c : process is + + -- code from book: + + subtype name is string(1 to 20); + type display_string is array (integer range 0 to 19) of character; + + variable item_name : name; + variable display : display_string; + + -- + + subtype big_endian_upper_halfword is bit_vector(0 to 15); + subtype little_endian_upper_halfword is bit_vector(31 downto 16); + + variable big : big_endian_upper_halfword; + variable little : little_endian_upper_halfword; + + -- end of code from book + + begin + + -- error: Incompatible types for assignment + -- display := item_name; -- ilegal + + item_name := (others => 'A'); + + little := x"AAAA"; + + -- code from book: + + display := display_string(item_name); + + -- + + big := little; + little := big; + + -- end of code from book + + wait; + end process process_3_c; + + + ---------------- + + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_16.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_16.vhd new file mode 100644 index 0000000..3ffbd2c --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_16.vhd @@ -0,0 +1,106 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity inline_16 is + +end entity inline_16; + + +---------------------------------------------------------------- + + +architecture test of inline_16 is + + -- code from book: + + type time_stamp is record + seconds : integer range 0 to 59; + minutes : integer range 0 to 59; + hours : integer range 0 to 23; + end record time_stamp; + + -- end of code from book + +begin + + + process_4_a : process is + + -- code from book: + + variable sample_time, current_time : time_stamp; + + -- + + constant midday : time_stamp := (0, 0, 12); + + -- end of code from book + + constant clock : integer := 79; + variable sample_hour : integer; + + begin + + current_time := (30, 15, 2); + + -- code from book: + + sample_time := current_time; + + sample_hour := sample_time.hours; + + current_time.seconds := clock mod 60; + + -- end of code from book + + wait; + end process process_4_a; + + + process_4_b : process is + + type opcodes is (add, sub, addu, subu, jmp, breq, brne, ld, st, nop); + type reg_number is range 0 to 31; + + type instruction is record + opcode : opcodes; + source_reg1, source_reg2, dest_reg : reg_number; + displacement : integer; + end record instruction; + + -- code from book: + + constant midday : time_stamp := (hours => 12, minutes => 0, seconds => 0); + + -- + + constant nop_instr : instruction := + ( opcode => addu, + source_reg1 | source_reg2 | dest_reg => 0, + displacement => 0 ); + + variable latest_event : time_stamp := (others => 0); -- initially midnight + + -- end of code from book + + begin + wait; + end process process_4_b; + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_17a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_17a.vhd new file mode 100644 index 0000000..a3f4a69 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_17a.vhd @@ -0,0 +1,46 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity inline_17a is + +end entity inline_17a; + + +---------------------------------------------------------------- + + +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +architecture test of inline_17a is + + -- code from book: + + nature electrical_bus is record + strobe : electrical; + bus_lines : electrical_vector(0 to 15); + end record electrical_bus; + + terminal address_bus, data_bus : electrical_bus; + + quantity data_voltages across data_currents through data_bus; + + -- end of code from book + +begin +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/modem_controller.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/modem_controller.vhd new file mode 100644 index 0000000..3a4af64 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/modem_controller.vhd @@ -0,0 +1,85 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity modem_controller is + +end entity modem_controller; + + +---------------------------------------------------------------- + + +architecture test of modem_controller is +begin + + -- code from book: + + modem_controller : process is + + type symbol is ('a', 't', 'd', 'h', digit, cr, other); + type symbol_string is array (1 to 20) of symbol; + type state is range 0 to 6; + type transition_matrix is array (state, symbol) of state; + + constant next_state : transition_matrix := + ( 0 => ('a' => 1, others => 6), + 1 => ('t' => 2, others => 6), + 2 => ('d' => 3, 'h' => 5, others => 6), + 3 => (digit => 4, others => 6), + 4 => (digit => 4, cr => 0, others => 6), + 5 => (cr => 0, others => 6), + 6 => (cr => 0, others => 6) ); + + variable command : symbol_string; + variable current_state : state := 0; + + -- not in book: + type sample_array is array (positive range <>) of symbol_string; + constant sample_command : sample_array := + ( 1 => ( 'a', 't', 'd', digit, digit, cr, others => other ), + 2 => ( 'a', 't', 'h', cr, others => other ), + 3 => ( 'a', 't', other, other, cr, others => other ) ); + -- end not in book + + begin + -- . . . + -- not in book: + for command_index in sample_command'range loop + command := sample_command(command_index); + -- end not in book + for index in 1 to 20 loop + current_state := next_state( current_state, command(index) ); + case current_state is + -- . . . + -- not in book: + when 0 => exit; + when others => null; + -- end not in book + end case; + end loop; + -- . . . + -- not in book: + end loop; + wait; + -- end not in book + end process modem_controller; + + -- end of code from book + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/tb_and_multiple.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/tb_and_multiple.vhd new file mode 100644 index 0000000..6723631 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/tb_and_multiple.vhd @@ -0,0 +1,58 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity tb_and_multiple is + +end entity tb_and_multiple; + + +---------------------------------------------------------------- + + +architecture test_behavioral of tb_and_multiple is + + -- code from book: + + signal count_value : bit_vector(7 downto 0); + signal terminal_count : bit; + + -- end of code from book + +begin + + -- code from book: + + tc_gate : entity work.and_multiple(behavioral) + port map ( i => count_value, y => terminal_count); + + -- end of code from book + + stumulus : process is + begin + wait for 10 ns; + count_value <= "10000000"; wait for 10 ns; + count_value <= "11111110"; wait for 10 ns; + count_value <= "01111111"; wait for 10 ns; + count_value <= "11111111"; wait for 10 ns; + count_value <= "00000000"; wait for 10 ns; + + wait; + end process stumulus; + +end architecture test_behavioral; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/tb_byte_swap.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/tb_byte_swap.vhd new file mode 100644 index 0000000..865378a --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/tb_byte_swap.vhd @@ -0,0 +1,50 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity tb_byte_swap is + +end entity tb_byte_swap; + + +---------------------------------------------------------------- + + +use work.byte_swap_types.all; + + +architecture test_behavior of tb_byte_swap is + + signal input, output : halfword := x"0000"; + +begin + + dut : entity work.byte_swap(behavior) + port map ( input => input, output => output ); + + stumulus : process is + begin + wait for 10 ns; + input <= x"ff00"; wait for 10 ns; + input <= x"00ff"; wait for 10 ns; + input <= x"aa33"; wait for 10 ns; + + wait; + end process stumulus; + +end architecture test_behavior; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/tb_coeff_ram.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/tb_coeff_ram.vhd new file mode 100644 index 0000000..0b7fd1f --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/tb_coeff_ram.vhd @@ -0,0 +1,61 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity tb_coeff_ram is + +end entity tb_coeff_ram; + + +---------------------------------------------------------------- + + +architecture test_abstract of tb_coeff_ram is + + use work.coeff_ram_types.all; + + signal rd, wr : bit := '0'; + signal addr : coeff_ram_address := 0; + signal d_in, d_out : real := 0.0; + +begin + + dut : entity work.coeff_ram(abstract) + port map ( rd => rd, wr => wr, + addr => addr, + d_in => d_in, d_out => d_out ); + + stumulus : process is + + begin + wait for 100 ns; + + addr <= 10; d_in <= 10.0; wait for 10 ns; + wr <= '1'; wait for 10 ns; + d_in <= 20.0; wait for 10 ns; + wr <= '0'; wait for 70 ns; + + addr <= 20; wait for 10 ns; + rd <= '1'; wait for 10 ns; + addr <= 10; wait for 10 ns; + rd <= '0'; wait for 10 ns; + + wait; + end process stumulus; + +end architecture test_abstract; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/transmission_lines.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/transmission_lines.vhd new file mode 100644 index 0000000..200e587 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/transmission_lines.vhd @@ -0,0 +1,70 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- not in book + +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +package transmission_lines_types is + + type word is array (0 to 31) of bit; + + subtype bus_lines is integer range 0 to 31; + nature electrical_bus is array (bus_lines) of electrical; + +end package transmission_lines_types; + + + +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +use work.transmission_lines_types.all; + +-- end not in book + +entity transmission_lines is + port ( terminal data_bus : electrical_bus; + signal clk : in bit; signal data_out : out word ); +end entity transmission_lines; + +---------------------------------------------------------------- + +architecture abstract of transmission_lines is + constant threshold : voltage := 1.5; + quantity bus_voltages across bus_currents through + data_bus to electrical_ref; +begin + + logic_value_maps : process (clk) is + begin + if clk = '1' then + for index in bus_lines loop + if bus_voltages(index) > threshold then + data_out(index) <= '1'; + else + data_out(index) <= '0'; + end if; + end loop; + end if; + end process logic_value_maps; + + -- additional VHDL-AMS code to describe reflections and attenuation + -- ... + +end architecture abstract; |