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-rw-r--r--testsuite/gna/bug7186/bug.vhdl24
-rwxr-xr-xtestsuite/gna/bug7186/testsuite.sh9
2 files changed, 33 insertions, 0 deletions
diff --git a/testsuite/gna/bug7186/bug.vhdl b/testsuite/gna/bug7186/bug.vhdl
new file mode 100644
index 0000000..9587521
--- /dev/null
+++ b/testsuite/gna/bug7186/bug.vhdl
@@ -0,0 +1,24 @@
+library IEEE;
+use ieee.numeric_std.all;
+use ieee.std_logic_1164.all;
+
+-- A testbench has no ports.
+entity system is
+end system;
+
+architecture behav of system is
+ subtype entry is unsigned(7 downto 0);
+ type invect is array (natural range <>) of entry;
+ signal minimum : entry;
+ signal vec : invect(0 to 20);
+ function min(iv : invect) return entry is
+ begin
+ return iv(0);
+ end;
+begin
+ process
+ begin
+ minimum <= min(invect); -- should be vec not invect
+ wait;
+ end process;
+end behav;
diff --git a/testsuite/gna/bug7186/testsuite.sh b/testsuite/gna/bug7186/testsuite.sh
new file mode 100755
index 0000000..fada702
--- /dev/null
+++ b/testsuite/gna/bug7186/testsuite.sh
@@ -0,0 +1,9 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+analyze_failure bug.vhdl
+
+clean
+
+echo "Test successful"