3 files changed, 114 insertions, 0 deletions
diff --git a/testsuite/gna/bug20549/info.txt b/testsuite/gna/bug20549/info.txt
new file mode 100644
index 0000000..65f335e
--- /dev/null
+++ b/testsuite/gna/bug20549/info.txt
@@ -0,0 +1,38 @@
+$ ghdl_mcode -r tb --trace-signals --activity=all
+.tb(arch).c 7A616610  e8 --a- last_event=-9223372036854775807fs last_active=-9223372036854775807fs val='0'; drv='0'
+.tb(arch).u0@clkgen(arch).b 7A6235C0  e8 --a- last_event=-9223372036854775807fs last_active=-9223372036854775807fs val='0'; drv='0'
+.tb(arch).u0@clkgen(arch).a 7A6232F0  e8 --a- last_event=-9223372036854775807fs last_active=-9223372036854775807fs val='U'; drv='U'
+Now is 0ms +0
+.tb(arch).c 7A616610  e8 AEa- last_event=0ms last_active=0ms val='U'; drv='U'
+.tb(arch).u0@clkgen(arch).b 7A6235C0  e8 A-a- last_event=-9223372036854775807fs last_active=0ms val='0'; drv='U'
+.tb(arch).u0@clkgen(arch).a 7A6232F0  e8 AEa- last_event=0ms last_active=0ms val='0'; drv='0'
+Now is 0ms +1
+.tb(arch).c 7A616610  e8 AEa- last_event=0ms last_active=0ms val='0'; drv='0'
+.tb(arch).u0@clkgen(arch).b 7A6235C0  e8 A-a- last_event=-9223372036854775807fs last_active=0ms val='0'; drv='0'
+.tb(arch).u0@clkgen(arch).a 7A6232F0  e8 --a- last_event=0ms last_active=0ms val='0'; drv='0'
+Now is 1ns +0
+tb.vhdl:43:13:@1ns:(report note): good: C is '0' as expected
+.tb(arch).c 7A616610  e8 --a- last_event=0ms last_active=0ms val='0'; drv='0'
+.tb(arch).u0@clkgen(arch).b 7A6235C0  e8 --a- last_event=-9223372036854775807fs last_active=0ms val='0'; drv='0'
+.tb(arch).u0@clkgen(arch).a 7A6232F0  e8 --a- last_event=0ms last_active=0ms val='0'; drv='0'
+Now is 10ns +0
+.tb(arch).c 7A616610  e8 --a- last_event=0ms last_active=0ms val='0'; drv='0'
+.tb(arch).u0@clkgen(arch).b 7A6235C0  e8 --a- last_event=-9223372036854775807fs last_active=0ms val='0'; drv='0'
+.tb(arch).u0@clkgen(arch).a 7A6232F0  e8 AEa- last_event=10ns last_active=10ns val='1'; drv='1'
+Now is 10ns +1
+.tb(arch).c 7A616610  e8 AEa- last_event=10ns last_active=10ns val='1'; drv='1'
+.tb(arch).u0@clkgen(arch).b 7A6235C0  e8 A-a- last_event=-9223372036854775807fs last_active=10ns val='0'; drv='1'
+.tb(arch).u0@clkgen(arch).a 7A6232F0  e8 --a- last_event=10ns last_active=10ns val='1'; drv='1'
+Now is 20ns +0
+.tb(arch).c 7A616610  e8 --a- last_event=10ns last_active=10ns val='1'; drv='1'
+.tb(arch).u0@clkgen(arch).b 7A6235C0  e8 --a- last_event=-9223372036854775807fs last_active=10ns val='0'; drv='1'
+.tb(arch).u0@clkgen(arch).a 7A6232F0  e8 AEa- last_event=20ns last_active=20ns val='0'; drv='0'
+Now is 20ns +1
+tb.vhdl:56:13:@20ns:(report note): good: C is '0' as expected
+.tb(arch).c 7A616610  e8 AEa- last_event=20ns last_active=20ns val='0'; drv='0'
+.tb(arch).u0@clkgen(arch).b 7A6235C0  e8 A-a- last_event=-9223372036854775807fs last_active=20ns val='0'; drv='0'
+.tb(arch).u0@clkgen(arch).a 7A6232F0  e8 --a- last_event=20ns last_active=20ns val='0'; drv='0'
+Now is 9223372036854775807fs +0
+.tb(arch).c 7A616610  e8 --a- last_event=20ns last_active=20ns val='0'; drv='0'
+.tb(arch).u0@clkgen(arch).b 7A6235C0  e8 --a- last_event=-9223372036854775807fs last_active=20ns val='0'; drv='0'
+.tb(arch).u0@clkgen(arch).a 7A6232F0  e8 --a- last_event=20ns last_active=20ns val='0'; drv='0'
diff --git a/testsuite/gna/bug20549/tb.vhdl b/testsuite/gna/bug20549/tb.vhdl
new file mode 100644
index 0000000..aa5e8e6
--- /dev/null
+++ b/testsuite/gna/bug20549/tb.vhdl
@@ -0,0 +1,66 @@
+
+-- This testbench fails with GHDL 0.29 and with GHDL svn_2013-02-13.
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity clkgen is
+
+    -- NOTE: Removing the default value makes the testbench work as expected.
+    port ( b: out std_ulogic := '0' );
+
+end entity;
+
+architecture arch of clkgen is
+    signal a: std_ulogic;
+begin
+    a <= '0', '1' after 10 ns, '0' after 20 ns;
+    b <= a;
+end architecture;
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity tb is
+end entity;
+
+architecture arch of tb is
+
+    -- NOTE: Declaring C as std_ulogic makes the testbench work as expected.
+    signal c: std_logic;
+
+begin
+
+    u0: entity work.clkgen port map ( b => c );
+
+    process
+    begin
+
+        wait for 1 ns;
+
+        if c = '0' then
+            report "good: C is '0' as expected";
+        else
+            -- This fails with GHDL 0.29.
+            report "BAD: C is not '0'" severity failure;
+        end if;
+
+        wait until c = '1' for 50 ns;
+        -- This is ok with GHDL 0.29.
+        assert c = '1' severity failure;
+
+        wait until c = '0' for 50 ns;
+
+        if c = '0' then
+            report "good: C is '0' as expected";
+        else
+            -- This fails with GHDL 0.29.
+            report "BAD: C is not '0'" severity failure;
+        end if;
+
+        wait;
+    end process;
+
+end architecture;
+
diff --git a/testsuite/gna/bug20549/testsuite.sh b/testsuite/gna/bug20549/testsuite.sh
new file mode 100755
index 0000000..4ee9e99
--- /dev/null
+++ b/testsuite/gna/bug20549/testsuite.sh
@@ -0,0 +1,10 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+analyze tb.vhdl
+elab_simulate tb
+
+clean
+
+echo "Test successful"