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diff --git a/testsuite/gna/bug16/repro1.vhdl b/testsuite/gna/bug16/repro1.vhdl
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+entity repro is
+end repro;
+
+entity comp is
+ port (s : bit);
+end comp;
+
+architecture behav of repro is
+ component comp is
+ port (s : bit);
+ end component;
+ signal s : bit;
+begin
+ c : comp port map (s);
+end behav;
+
+use work.pkg.all;
+entity comp2 is
+ port (s : bit);
+end comp2;
+
+architecture behav of comp is
+ component comp2 is
+ port (s : bit);
+ end component;
+begin
+ c2: comp2 port map (s);
+end behav;