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-rw-r--r--parse.adb22
-rw-r--r--sem_psl.adb3
-rw-r--r--testsuite/gna/ticket18/Makefile18
-rw-r--r--testsuite/gna/ticket18/psl_test_error.vhd53
-rw-r--r--testsuite/gna/ticket18/psl_test_working.vhd53
-rwxr-xr-xtestsuite/gna/ticket18/testsuite.sh13
6 files changed, 161 insertions, 1 deletions
diff --git a/parse.adb b/parse.adb
index 24ae821..a6351d8 100644
--- a/parse.adb
+++ b/parse.adb
@@ -5642,11 +5642,31 @@ package body Parse is
begin
Res := Create_Iir (Iir_Kind_Psl_Assert_Statement);
Scanner.Flag_Psl := True;
+
+ -- Skip 'assert'
Scan;
+
Set_Psl_Property (Res, Parse_Psl.Parse_Psl_Property);
+
+ -- No more PSL tokens after the property.
+ Scanner.Flag_Psl := False;
+
+ if Current_Token = Tok_Report then
+ -- Skip 'report'
+ Scan;
+
+ Set_Report_Expression (Res, Parse_Expression);
+ end if;
+
+ if Current_Token = Tok_Severity then
+ -- Skip 'severity'
+ Scan;
+
+ Set_Severity_Expression (Res, Parse_Expression);
+ end if;
+
Expect (Tok_Semi_Colon);
Scanner.Flag_Scan_In_Comment := False;
- Scanner.Flag_Psl := False;
return Res;
end Parse_Psl_Assert_Statement;
diff --git a/sem_psl.adb b/sem_psl.adb
index a16da57..15b924c 100644
--- a/sem_psl.adb
+++ b/sem_psl.adb
@@ -474,6 +474,9 @@ package body Sem_Psl is
Extract_Clock (Prop, Clk);
Set_Psl_Property (Stmt, Prop);
+ -- Sem report and severity expressions.
+ Sem_Report_Statement (Stmt);
+
-- Properties must be clocked.
if Clk = Null_Node then
if Current_Psl_Default_Clock = Null_Iir then
diff --git a/testsuite/gna/ticket18/Makefile b/testsuite/gna/ticket18/Makefile
new file mode 100644
index 0000000..1c3a056
--- /dev/null
+++ b/testsuite/gna/ticket18/Makefile
@@ -0,0 +1,18 @@
+psl_test_working: psl_test_working.vhd
+ ghdl -a --std=02 -fpsl psl_test_working.vhd
+ ghdl -e --std=02 -fpsl psl_test_working
+ ./psl_test_working --stop-time=200ns
+
+psl_test_error: psl_test_error.vhd
+ ghdl -a --std=02 -fpsl psl_test_error.vhd
+ ghdl -e --std=02 -fpsl psl_test_error
+ ./psl_test_error --stop-time=200ns
+
+all: clean psl_test_working psl_test_error
+
+.PHONY: clean
+clean:
+ rm -f *.cf
+ rm -f *.o
+ rm -f psl_test_working
+ rm -f psl_test_error \ No newline at end of file
diff --git a/testsuite/gna/ticket18/psl_test_error.vhd b/testsuite/gna/ticket18/psl_test_error.vhd
new file mode 100644
index 0000000..aff4362
--- /dev/null
+++ b/testsuite/gna/ticket18/psl_test_error.vhd
@@ -0,0 +1,53 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+
+entity psl_test_error is
+end entity psl_test_error;
+
+
+architecture test of psl_test_error is
+
+
+ signal s_rst_n : std_logic := '0';
+ signal s_clk : std_logic := '0';
+ signal s_write : std_logic;
+ signal s_read : std_logic;
+
+
+begin
+
+
+ s_rst_n <= '1' after 100 ns;
+ s_clk <= not s_clk after 10 ns;
+
+
+ TestP : process is
+ begin
+ report "RUNNING PSL_TEST_ERROR test case";
+ report "================================";
+ s_write <= '0';
+ s_read <= '0';
+ wait until s_rst_n = '1' and rising_edge(s_clk);
+ s_write <= '1'; -- cover should hit
+ wait until rising_edge(s_clk);
+ s_read <= '1'; -- assertion should hit
+ wait until rising_edge(s_clk);
+ s_write <= '0';
+ s_read <= '0';
+ wait;
+ end process TestP;
+
+
+
+ -- psl statements
+
+ -- psl default clock is rising_edge(s_clk);
+
+ -- this don't work (error while analyse)
+ -- psl assert always (s_write -> not(s_read)) report "ERROR: s_write and s_read active @ same time!";
+
+
+end architecture test; \ No newline at end of file
diff --git a/testsuite/gna/ticket18/psl_test_working.vhd b/testsuite/gna/ticket18/psl_test_working.vhd
new file mode 100644
index 0000000..acb8aae
--- /dev/null
+++ b/testsuite/gna/ticket18/psl_test_working.vhd
@@ -0,0 +1,53 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+
+entity psl_test_working is
+end entity psl_test_working;
+
+
+architecture test of psl_test_working is
+
+
+ signal s_rst_n : std_logic := '0';
+ signal s_clk : std_logic := '0';
+ signal s_write : std_logic;
+ signal s_read : std_logic;
+
+
+begin
+
+
+ s_rst_n <= '1' after 100 ns;
+ s_clk <= not s_clk after 10 ns;
+
+
+ TestP : process is
+ begin
+ report "RUNNING PSL_TEST_WORKING test case";
+ report "==================================";
+ s_write <= '0';
+ s_read <= '0';
+ wait until s_rst_n = '1' and rising_edge(s_clk);
+ s_write <= '1'; -- cover should hit
+ wait until rising_edge(s_clk);
+ s_read <= '1'; -- assertion should hit
+ wait until rising_edge(s_clk);
+ s_write <= '0';
+ s_read <= '0';
+ wait;
+ end process TestP;
+
+
+
+ -- psl statements
+
+ -- psl default clock is rising_edge(s_clk);
+
+ -- this one works:
+ -- psl assert always (s_write -> not(s_read));
+
+
+end architecture test; \ No newline at end of file
diff --git a/testsuite/gna/ticket18/testsuite.sh b/testsuite/gna/ticket18/testsuite.sh
new file mode 100755
index 0000000..86192a5
--- /dev/null
+++ b/testsuite/gna/ticket18/testsuite.sh
@@ -0,0 +1,13 @@
+#!/bin/sh
+
+. ../../testenv.sh
+
+GHDL_FLAGS="-fpsl --std=02"
+
+analyze psl_test_error.vhd
+elab_simulate psl_test_error --stop-time=200ns
+
+analyze psl_test_working.vhd
+elab_simulate psl_test_working --stop-time=200ns
+
+clean \ No newline at end of file