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path: root/src/SubcircuitLibrary/7485/c_gate.pro
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update=03/26/19 19:06:59
version=1
last_client=eeschema
[general]
version=1
RootSch=
BoardNm=
[pcbnew]
version=1
LastNetListRead=
UseCmpFile=1
PadDrill=0.600000000000
PadDrillOvalY=0.600000000000
PadSizeH=1.500000000000
PadSizeV=1.500000000000
PcbTextSizeV=1.500000000000
PcbTextSizeH=1.500000000000
PcbTextThickness=0.300000000000
ModuleTextSizeV=1.000000000000
ModuleTextSizeH=1.000000000000
ModuleTextSizeThickness=0.150000000000
SolderMaskClearance=0.000000000000
SolderMaskMinWidth=0.000000000000
DrawSegmentWidth=0.200000000000
BoardOutlineThickness=0.100000000000
ModuleOutlineThickness=0.150000000000
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
LibName1=texas
LibName2=intel
LibName3=audio
LibName4=interface
LibName5=digital-audio
LibName6=philips
LibName7=display
LibName8=cypress
LibName9=siliconi
LibName10=opto
LibName11=atmel
LibName12=contrib
LibName13=valves
LibName14=eSim_Analog
LibName15=eSim_Devices
LibName16=eSim_Digital
LibName17=eSim_Hybrid
LibName18=eSim_Miscellaneous
LibName19=eSim_Plot
LibName20=eSim_Power
LibName21=eSim_PSpice
LibName22=eSim_Sources
LibName23=eSim_Subckt
LibName24=eSim_User