path: root/Windows/spice/examples/tclspice/tcl-testbench3/FB14.cir

* gnetlist -g spice-sdb -o tmp.lst FB14_batterie.sch
*********************************************************
* Spice file generated by gnetlist                      *
* spice-sdb version 12.27.2005 by SDB --                *
* provides advanced spice netlisting capability.        *
* Documentation at http://www.brorson.com/gEDA/SPICE/   *
*********************************************************
*vvvvvvvv  Included SPICE model from models/tl431.cir vvvvvvvv
* modele du TL431
.subckt TL431-R REFIN ANODE CATHODE
Q8 Q2_C Q2_C R4_N 0 P1
Q9 CATHODE Q7_C Q9_E 0 n1
R8 Q4_E ANODE 800
R9 Q2_E R9_N 4k
Q10 CATHODE R6_P ANODE 0 n1 5
Q11 Q7_C R10_P ANODE 0 n1
*.nodeset R3_N 1
C2 R9_N C2_N 20p
R10 R10_P R1_N 1k
C1 CATHODE Q7_C 20p
D1 ANODE Q7_C DIODE
D2 ANODE CATHODE DIODE
R4 CATHODE R4_N 800
Q2 Q2_C Q1_E Q2_E 0 n1
Q3 R9_N C2_N ANODE 0 n1
R5 CATHODE R5_N 800
R6 R6_P Q9_E 150
Q1 CATHODE REFIN Q1_E 0 n1
R7 ANODE R6_P 10k
Q6 Q7_C Q7_C REFIN 0 n1
Q7 Q7_C Q2_C R5_N 0 P1
R1 R3_N R1_N 2.4k
R2 R3_N C2_N 7.2k
Q4 C2_N R1_N Q4_E 0 n1
Q5 R1_N R1_N ANODE 0 n1
R3 Q1_E R3_N 3.28k
.model p1 pnp bf=50
.model n1 npn bf=100 tf=2n cjc=1p is=5e-18 NF=1.07
.model diode d rs=1 cjo=2p
.ends 
*^^^^^^^^  End of included SPICE model from models/tl431.cir ^^^^^^^^
*
*vvvvvvvv  Included SPICE model from models/irf4905.spi vvvvvvvv
.SUBCKT irf4905 1 2 3
**************************************
*      Model Generated by MODPEX     *
*Copyright(c) Symmetry Design Systems*
*         All Rights Reserved        *
*    UNPUBLISHED LICENSED SOFTWARE   *
*   Contains Proprietary Information *
*      Which is The Property of      *
*     SYMMETRY OR ITS LICENSORS      *
*Commercial Use or Resale Restricted *
*   by Symmetry License Agreement    *
**************************************
* Model generated on Jun 19, 96
* Model format: SPICE3
* Symmetry POWER MOS Model (Version 1.0)
* External Node Designations
* Node 1 -> Drain
* Node 2 -> Gate
* Node 3 -> Source
M1 9 7 8 8 MM L=100u W=100u
* Default values used in MM:
* The voltage-dependent capacitances are
* not included. Other default values are:
*   RS=0 RD=0 LD=0 CBD=0 CBS=0 CGBO=0
.MODEL MM PMOS LEVEL=1 IS=1e-32
+VTO=-3.53713 LAMBDA=0.00549383 KP=23.3701
+CGSO=2.84439e-05 CGDO=1e-11
RS 8 3 0.0101265
D1 1 3 MD
.MODEL MD D IS=1.29014e-08 RS=0.00297795 N=1.46717 BV=55
+IBV=0.00025 EG=1.2 XTI=4 TT=0
+CJO=3.56968e-09 VJ=1.17553 M=0.500933 FC=0.5
RDS 3 1 2.2e+06
RD 9 1 0.0001
RG 2 7 6
D2 5 4 MD1
* Default values used in MD1:
*   RS=0 EG=1.11 XTI=3.0 TT=0
*   BV=infinite IBV=1mA
.MODEL MD1 D IS=1e-32 N=50
+CJO=4.83772e-09 VJ=0.625334 M=0.543532 FC=1e-08
D3 5 0 MD2
* Default values used in MD2:
*   EG=1.11 XTI=3.0 TT=0 CJO=0
*   BV=infinite IBV=1mA
.MODEL MD2 D IS=1e-10 N=0.4 RS=3e-06
RL 5 10 1
FI2 7 9 VFI2 -1
VFI2 4 0 0
EV16 10 0 9 7 1
CAP 11 10 6.08035e-09
FI1 7 9 VFI1 -1
VFI1 11 6 0
RCAP 6 10 1
D4 6 0 MD3
* Default values used in MD3:
*   EG=1.11 XTI=3.0 TT=0 CJO=0
*   RS=0 BV=infinite IBV=1mA
.MODEL MD3 D IS=1e-10 N=0.4
.ENDS

*^^^^^^^^  End of included SPICE model from models/irf4905.spi ^^^^^^^^
*
*vvvvvvvv  Included SPICE model from models/LM2902.MOD vvvvvvvv
*//////////////////////////////////////////////////////////////////////
* (C) National Semiconductor, Inc.
* Models developed and under copyright by:
* National Semiconductor, Inc.  

*/////////////////////////////////////////////////////////////////////
* Legal Notice: This material is intended for free software support.
* The file may be copied, and distributed; however, reselling the 
*  material is illegal

*////////////////////////////////////////////////////////////////////
* For ordering or technical information on these models, contact:
* National Semiconductor's Customer Response Center
*                 7:00 A.M.--7:00 P.M.  U.S. Central Time
*                                (800) 272-9959
* For Applications support, contact the Internet address:
*  amps-apps@galaxy.nsc.com

*//////////////////////////////////////////////////////////
*LM2902 QUAD OPERATIONAL AMPLIFIER MACRO-MODEL
*//////////////////////////////////////////////////////////
*
* connections:      non-inverting input
*                   |   inverting input
*                   |   |   positive power supply
*                   |   |   |   negative power supply
*                   |   |   |   |   output
*                   |   |   |   |   |
*                   |   |   |   |   |
.SUBCKT LM2902/NS   1   2  99  50  28
*
*Features:
*Eliminates need for dual supplies
*Large DC voltage gain =             100dB
*High bandwidth =       1MHz
*Low input offset voltage =            2mV
*Wide supply range =        +-1.5V to +-16V
*
*NOTE: Model is for single device only and simulated
*      supply current is 1/4 of total device current.
*      Output crossover distortion with dual supplies
*      is not modeled.
*
****************INPUT STAGE**************
*
IOS 2 1 5N
*^Input offset current
R1 1 3 500K
R2 3 2 500K
I1 99 4 100U
R3 5 50 517
R4 6 50 517
Q1 5 2 4 QX
Q2 6 7 4 QX
*Fp2=1.2 MHz
C4 5 6 128.27P
*
***********COMMON MODE EFFECT***********
*
I2 99 50 75U
*^Quiescent supply current
EOS 7 1 POLY(1) 16 49 2E-3 1
*Input offset voltage.^
R8 99 49 60K
R9 49 50 60K
*
*********OUTPUT VOLTAGE LIMITING********
V2 99 8 1.63
D1 9 8 DX
D2 10 9 DX
V3 10 50 .635
*
**************SECOND STAGE**************
*
EH 99 98 99 49 1
G1 98 9 POLY(1) 5 6 0 9.8772E-4 0 .3459
*Fp1=7.86 Hz
R5 98 9 101.2433MEG
C3 98 9 200P
*
***************POLE STAGE***************
*
*Fp=2 MHz
G3 98 15 9 49 1E-6
R12 98 15 1MEG
C5 98 15 7.9577E-14
*
*********COMMON-MODE ZERO STAGE*********
*
*Fpcm=10 KHz
G4 98 16 3 49 5.6234E-8
L2 98 17 15.9M
R13 17 16 1K
*
**************OUTPUT STAGE**************
*
F6 50 99 POLY(1) V6 300U 1
E1 99 23 99 15 1
R16 24 23 17.5
D5 26 24 DX
V6 26 22 .63V
R17 23 25 17.5
D6 25 27 DX
V7 22 27 .63V
V5 22 21 0.27V
D4 21 15 DX
V4 20 22 0.27V
D3 15 20 DX
L3 22 28 500P
RL3 22 28 100K
*
***************MODELS USED**************
*
.MODEL DX D(IS=1E-15)
.MODEL QX PNP(BF=1.111E3)
*
.ENDS
*$
*^^^^^^^^  End of included SPICE model from models/LM2902.MOD ^^^^^^^^
*
*vvvvvvvv  Included SPICE model from models/bas70.mod vvvvvvvv
*
.SUBCKT BAS70 1 3 
* The Resistor R1 does not reflect 
* a physical device.  Instead it 
* improves modeling in the reverse
* mode of operation.
R1 1 3 1.409E+09 
D1 1 3 modBAS70 
.MODEL modBAS70 D( 
+ IS = 3.22E-09 
+ N = 1.018 
+ BV = 77
*+ IBV = 1.67E-07 
+ IBV = 10E-06 
+ RS = 20.89 
+ CJO = 1.655E-12 
+ VJ = 0.349
+ M = 0.3583
+ FC = 0.5 
+ TT = 0 
+ EG = 0.69 
+ XTI = 2) 
.ENDS
*
*^^^^^^^^  End of included SPICE model from models/bas70.mod ^^^^^^^^
*
*vvvvvvvv  Included SPICE model from models/BC547B.spi vvvvvvvv
*
.MODEL QBC547B NPN( 
+     IS=2.39E-14
+     NF=1.008
+     ISE=3.545E-15
+     NE=1.541
+     BF=294.3
+     IKF=0.1357
+     VAF=63.2
+     NR=1.004
+     ISC=6.272E-14
+     NC=1.243
+     BR=7.946
+     IKR=0.1144
+     VAR=25.9
+     RB=1
+     IRB=1E-06
+     RBM=1
+     RE=0.4683
+     RC=0.85
+     XTB=0
+     EG=1.11
+     XTI=3
+     CJE=1.358E-11
+     VJE=0.65
+     MJE=0.3279
+     TF=4.391E-10
+     XTF=120
+     VTF=2.643
+     ITF=0.7495
+     PTF=0
+     CJC=3.728E-12
+     VJC=0.3997
+     MJC=0.2955
+     XCJC=0.6193
+     TR=1E-32
+     CJS=0
+     VJS=0.75
+     MJS=0.333
+     FC=0.9579 )
*
*^^^^^^^^  End of included SPICE model from models/BC547B.spi ^^^^^^^^
*
*vvvvvvvv  Included SPICE model from models/LM293.5_1 vvvvvvvv
* LM293 VOLTAGE COMPARATOR "MACROMODEL" SUBCIRCUIT
* CREATED USING PARTS VERSION 4.03 ON 03/07/90 AT 14:17
* REV (N/A)
* CONNECTIONS:   NON-INVERTING INPUT
*                | INVERTING INPUT
*                | | POSITIVE POWER SUPPLY
*                | | | NEGATIVE POWER SUPPLY
*                | | | | OPEN COLLECTOR OUTPUT
*                | | | | |
.SUBCKT LM293    1 2 3 4 5
*
  F1    9  3 V1 1
  IEE   3  7 DC 100.0E-6
  VI1  21  1 DC .75
  VI2  22  2 DC .75
  Q1    9 21  7 QIN
  Q2    8 22  7 QIN
  Q3    9  8  4 QMO
  Q4    8  8  4 QMI
.MODEL QIN PNP(IS=800.0E-18 BF=2.000E3)
.MODEL QMI NPN(IS=800.0E-18 BF=1002)
.MODEL QMO NPN(IS=800.0E-18 BF=1000 CJC=1E-15 TR=807.4E-9)
  E1   10  4  9  4  1
  V1   10 11 DC 0
  Q5    5 11  4 QOC
.MODEL QOC NPN(IS=800.0E-18 BF=20.29E3 CJC=1E-15 TF=942.6E-12 TR=543.8E-9)
  DP    4  3 modDX
  RP 3  4 46.3E3
.MODEL modDX  D(IS=800.0E-18)
*
.ENDS

*^^^^^^^^  End of included SPICE model from models/LM293.5_1 ^^^^^^^^
*
*vvvvvvvv  Included SPICE model from models/NTD18N06L.REV0.SP3 vvvvvvvv
.SUBCKT ntd18n06l 1 2 3
**************************************
*      Model Generated by MODPEX     *
*Copyright(c) Symmetry Design Systems*
*         All Rights Reserved        *
*    UNPUBLISHED LICENSED SOFTWARE   *
*   Contains Proprietary Information *
*      Which is The Property of      *
*     SYMMETRY OR ITS LICENSORS      *
*Commercial Use or Resale Restricted *
*   by Symmetry License Agreement    *
**************************************
* Model generated on Aug  3, 04
* MODEL FORMAT: SPICE3
* Symmetry POWER MOS Model (Version 1.0)
* External Node Designations
* Node 1 -> Drain
* Node 2 -> Gate
* Node 3 -> Source
M1 9 7 8 8 MM L=100u W=100u
* Default values used in MM:
* The voltage-dependent capacitances are
* not included. Other default values are:
*   RS=0 RD=0 LD=0 CBD=0 CBS=0 CGBO=0
.MODEL MM NMOS LEVEL=1 IS=1e-32
+VTO=1.98948 LAMBDA=0 KP=21.272
+CGSO=4.18085e-06 CGDO=8.56633e-08
RS 8 3 0.0375073
D1 3 1 MD
.MODEL MD D IS=8.82716e-09 RS=0.00616994 N=1.5 BV=60
+IBV=0.00025 EG=1 XTI=2.2423 TT=0
+CJO=5.77207e-10 VJ=0.656334 M=0.448458 FC=0.5
RDS 3 1 2.4e+11
RD 9 1 0.0001
RG 2 7 17.1584
D2 4 5 MD1
* Default values used in MD1:
*   RS=0 EG=1.11 XTI=3.0 TT=0
*   BV=infinite IBV=1mA
.MODEL MD1 D IS=1e-32 N=50
+CJO=6.54462e-10 VJ=1.69471 M=0.891807 FC=1e-08
D3 0 5 MD2
* Default values used in MD2:
*   EG=1.11 XTI=3.0 TT=0 CJO=0
*   BV=infinite IBV=1mA
.MODEL MD2 D IS=1e-10 N=0.400114 RS=3e-06
RL 5 10 1
FI2 7 9 VFI2 -1
VFI2 4 0 0
EV16 10 0 9 7 1
CAP 11 10 6.54462e-10
FI1 7 9 VFI1 -1
VFI1 11 6 0
RCAP 6 10 1
D4 0 6 MD3
* Default values used in MD3:
*   EG=1.11 XTI=3.0 TT=0 CJO=0
*   RS=0 BV=infinite IBV=1mA
.MODEL MD3 D IS=1e-10 N=0.400114
.ENDS ntd18n06l

*^^^^^^^^  End of included SPICE model from models/NTD18N06L.REV0.SP3 ^^^^^^^^
*
*==============  Begin SPICE netlist of main design ============
X10 iimage vertsup Vcc 0 ledverte LM293
R20 vmbatm 1 10k  
*.INCLUDE models/NTD18N06L.REV0.SP3
*.INCLUDE models/LM293.5_1
R33 Imbat V9p 100  
*.INCLUDE models/BC547B.spi
R32 V9p 0 10k  
*.INCLUDE models/bas70.mod
R31 ledverte Vcc 22k  
*.INCLUDE models/LM2902.MOD
R30 ledrouge Vcc 22k  
*.INCLUDE models/irf4905.spi
*.INCLUDE models/tl431.cir
Vbat 2 vmbatm DC 9V
V3 3 0 DC 6V
R? 0 Vcc 2.2k  
R19 vmbat Vs2 22k  
V1 Vcc 0 DC 26V
R18 Vs2 Vcc 2.2k  
R17 vref2 0 430  
R16 v7m Vs2 100k  
X9 V9p V9m Vcc 0 Iimage LM2902/NS
R15 iimage v7m 100  
R14 vmbat imbat 0.1  
X8 vcc 1 BAS70
R9 Vcc vref1 2.2k  
R29 0 vertsup 1K  
X7 vref2 v7m Vcc 0 Vs2 LM293
R8 V2p Vs2 100k  
R13 Vcc vref_temp 2.2k  
R28 vertsup ledrouge 22k  
X6 Vcc Vs2 imbat ntd18n06l
R7 V2p Vimage 1k  
R12 0 Vtest_temp 6.05k  
R27 rougesup rougeinf 20k  
X5 0 1 vmbatm ntd18n06l
R6 vref2 Vtest1 660  
R11 Vtest_temp vref_temp 10k  
R26 0 rougeinf 2.2k  
R10 Vtest_temp vref_temp 9.387k  
X4 Vtest1 0 vref1 TL431-R
R5 Vtest1 vref1 2.83k  
R25 3 rougesup 2.2k  
X3 Vtest_temp 0 vref_temp TL431-R
R4 0 v1p 22k  
Vvcc cmd_buck 0 DC 0V
R24 V9m Iimage 10k  
X2 vref_temp V2p Vcc 0 Vs2 LM293
R3 V1m Vimage 22k  
X13 ledrouge 4 BAS70
R23 Vmbat V9m 100  
X1 v1p V1m Vcc 0 Vimage LM2902/NS
R2 vref1 V1m 22k  
Rbat 2 vmbat 100  
X12 vimage rougeinf Vcc 0 4 LM293
R22 Vmbatm V1m 22k  
R1 vmbat v1p 22k  
X11 rougesup vimage Vcc 0 4 LM293
R21 0 v1p 22k  
.end