Examples/Halfwave_Rectifier/Halfwave_Rectifier.cir.out


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

* eeschema netlist version 1.1 (spice format) creation date: wed jul  1 11:15:52 2015

.include D.lib
d1 in out D1N750
r1  out gnd 1k
v1  in gnd sine(0 2 50 0 0)
.tran 10e-03 100e-03 0e-03

* Control Statements 
.control
run
print allv > plot_data_v.txt
print alli > plot_data_i.txt
.endc
.end