* Subcircuit 4_bit_FA .subckt 4_bit_FA net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ * c:\users\malli\esim\src\subcircuitlibrary\4_bit_fa\4_bit_fa.cir .include 4_and.sub .include 3_and.sub .include 4_OR.sub * u2 net-_u1-pad2_ net-_u1-pad3_ net-_u16-pad2_ d_or * u3 net-_u1-pad2_ net-_u1-pad3_ net-_u24-pad2_ d_and * u4 net-_u1-pad4_ net-_u1-pad5_ net-_u17-pad2_ d_or * u5 net-_u1-pad4_ net-_u1-pad5_ net-_u26-pad2_ d_and * u6 net-_u1-pad6_ net-_u1-pad7_ net-_u18-pad2_ d_or * u7 net-_u1-pad6_ net-_u1-pad7_ net-_u10-pad2_ d_and * u8 net-_u1-pad8_ net-_u1-pad9_ net-_u10-pad1_ d_or * u9 net-_u1-pad8_ net-_u1-pad9_ net-_u31-pad2_ d_and * u16 net-_u1-pad1_ net-_u16-pad2_ net-_u16-pad3_ d_and * u24 net-_u16-pad3_ net-_u24-pad2_ net-_u17-pad1_ d_or * u33 net-_u23-pad2_ net-_u24-pad2_ net-_u33-pad3_ d_or * u23 net-_u16-pad2_ net-_u23-pad2_ d_inverter * u38 net-_u1-pad1_ net-_u33-pad3_ net-_u38-pad3_ d_xor * u42 net-_u38-pad3_ net-_u1-pad13_ d_inverter * u17 net-_u17-pad1_ net-_u17-pad2_ net-_u17-pad3_ d_and * u26 net-_u17-pad3_ net-_u26-pad2_ net-_u18-pad1_ d_or * u34 net-_u25-pad2_ net-_u26-pad2_ net-_u34-pad3_ d_or * u25 net-_u17-pad2_ net-_u25-pad2_ d_inverter * u39 net-_u17-pad1_ net-_u34-pad3_ net-_u39-pad3_ d_xor * u44 net-_u39-pad3_ net-_u1-pad10_ d_inverter * u18 net-_u18-pad1_ net-_u18-pad2_ net-_u18-pad3_ d_and * u28 net-_u18-pad3_ net-_u10-pad2_ net-_u28-pad3_ d_or * u35 net-_u27-pad2_ net-_u10-pad2_ net-_u35-pad3_ d_or * u27 net-_u18-pad2_ net-_u27-pad2_ d_inverter * u40 net-_u18-pad1_ net-_u35-pad3_ net-_u40-pad3_ d_xor * u45 net-_u40-pad3_ net-_u1-pad11_ d_inverter * u31 net-_u21-pad2_ net-_u31-pad2_ net-_u31-pad3_ d_or * u21 net-_u10-pad1_ net-_u21-pad2_ d_inverter * u37 net-_u28-pad3_ net-_u31-pad3_ net-_u37-pad3_ d_xor * u43 net-_u37-pad3_ net-_u1-pad12_ d_inverter * u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_and * u32 net-_u1-pad1_ net-_u32-pad2_ net-_u32-pad3_ d_and * u41 net-_u32-pad3_ net-_u41-pad2_ net-_u1-pad14_ d_or x1 net-_u10-pad1_ net-_u18-pad2_ net-_u17-pad2_ net-_u16-pad2_ net-_u32-pad2_ 4_and x4 net-_u10-pad1_ net-_u18-pad2_ net-_u26-pad2_ net-_x3-pad3_ 3_and x2 net-_u10-pad1_ net-_u18-pad2_ net-_u17-pad2_ net-_u24-pad2_ net-_x2-pad5_ 4_and x3 net-_u31-pad2_ net-_u10-pad3_ net-_x3-pad3_ net-_x2-pad5_ net-_u41-pad2_ 4_OR a1 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u16-pad2_ u2 a2 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u24-pad2_ u3 a3 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u17-pad2_ u4 a4 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u26-pad2_ u5 a5 [net-_u1-pad6_ net-_u1-pad7_ ] net-_u18-pad2_ u6 a6 [net-_u1-pad6_ net-_u1-pad7_ ] net-_u10-pad2_ u7 a7 [net-_u1-pad8_ net-_u1-pad9_ ] net-_u10-pad1_ u8 a8 [net-_u1-pad8_ net-_u1-pad9_ ] net-_u31-pad2_ u9 a9 [net-_u1-pad1_ net-_u16-pad2_ ] net-_u16-pad3_ u16 a10 [net-_u16-pad3_ net-_u24-pad2_ ] net-_u17-pad1_ u24 a11 [net-_u23-pad2_ net-_u24-pad2_ ] net-_u33-pad3_ u33 a12 net-_u16-pad2_ net-_u23-pad2_ u23 a13 [net-_u1-pad1_ net-_u33-pad3_ ] net-_u38-pad3_ u38 a14 net-_u38-pad3_ net-_u1-pad13_ u42 a15 [net-_u17-pad1_ net-_u17-pad2_ ] net-_u17-pad3_ u17 a16 [net-_u17-pad3_ net-_u26-pad2_ ] net-_u18-pad1_ u26 a17 [net-_u25-pad2_ net-_u26-pad2_ ] net-_u34-pad3_ u34 a18 net-_u17-pad2_ net-_u25-pad2_ u25 a19 [net-_u17-pad1_ net-_u34-pad3_ ] net-_u39-pad3_ u39 a20 net-_u39-pad3_ net-_u1-pad10_ u44 a21 [net-_u18-pad1_ net-_u18-pad2_ ] net-_u18-pad3_ u18 a22 [net-_u18-pad3_ net-_u10-pad2_ ] net-_u28-pad3_ u28 a23 [net-_u27-pad2_ net-_u10-pad2_ ] net-_u35-pad3_ u35 a24 net-_u18-pad2_ net-_u27-pad2_ u27 a25 [net-_u18-pad1_ net-_u35-pad3_ ] net-_u40-pad3_ u40 a26 net-_u40-pad3_ net-_u1-pad11_ u45 a27 [net-_u21-pad2_ net-_u31-pad2_ ] net-_u31-pad3_ u31 a28 net-_u10-pad1_ net-_u21-pad2_ u21 a29 [net-_u28-pad3_ net-_u31-pad3_ ] net-_u37-pad3_ u37 a30 net-_u37-pad3_ net-_u1-pad12_ u43 a31 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 a32 [net-_u1-pad1_ net-_u32-pad2_ ] net-_u32-pad3_ u32 a33 [net-_u32-pad3_ net-_u41-pad2_ ] net-_u1-pad14_ u41 * Schematic Name: d_or, NgSpice Name: d_or .model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) * Schematic Name: d_and, NgSpice Name: d_and .model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) * Schematic Name: d_or, NgSpice Name: d_or .model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) * Schematic Name: d_and, NgSpice Name: d_and .model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) * Schematic Name: d_or, NgSpice Name: d_or .model u6 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) * Schematic Name: d_and, NgSpice Name: d_and .model u7 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) * Schematic Name: d_or, NgSpice Name: d_or .model u8 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) * Schematic Name: d_and, NgSpice Name: d_and .model u9 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) * Schematic Name: d_and, NgSpice Name: d_and .model u16 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) * Schematic Name: d_or, NgSpice Name: d_or .model u24 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) * Schematic Name: d_or, NgSpice Name: d_or .model u33 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u23 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) * Schematic Name: d_xor, NgSpice Name: d_xor .model u38 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u42 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) * Schematic Name: d_and, NgSpice Name: d_and .model u17 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) * Schematic Name: d_or, NgSpice Name: d_or .model u26 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) * Schematic Name: d_or, NgSpice Name: d_or .model u34 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u25 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) * Schematic Name: d_xor, NgSpice Name: d_xor .model u39 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u44 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) * Schematic Name: d_and, NgSpice Name: d_and .model u18 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) * Schematic Name: d_or, NgSpice Name: d_or .model u28 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) * Schematic Name: d_or, NgSpice Name: d_or .model u35 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u27 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) * Schematic Name: d_xor, NgSpice Name: d_xor .model u40 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u45 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) * Schematic Name: d_or, NgSpice Name: d_or .model u31 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u21 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) * Schematic Name: d_xor, NgSpice Name: d_xor .model u37 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u43 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) * Schematic Name: d_and, NgSpice Name: d_and .model u10 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) * Schematic Name: d_and, NgSpice Name: d_and .model u32 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) * Schematic Name: d_or, NgSpice Name: d_or .model u41 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) * Control Statements .ends 4_bit_FA