* c:\users\shanthipriya\esim-workspace\sn74ls90\sn74ls90.cir

.include 74ls90.sub
x1 net-_u4-pad2_ clock net-_u3-pad2_ net-_u1-pad2_ ? ? ? ? net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ net-_u10-pad4_ 74ls90
v3  net-_u2-pad1_ gnd pulse(0 5 0 1n 1n 5u 10u)
* u2  net-_u2-pad1_ clock adc_bridge_1
* u5  clock plot_v1
v1 net-_u1-pad1_ gnd  dc 5
* u1  net-_u1-pad1_ net-_u1-pad2_ adc_bridge_1
v2 net-_u3-pad1_ gnd  dc 1
* u3  net-_u3-pad1_ net-_u3-pad2_ adc_bridge_1
v4 net-_u4-pad1_ gnd  dc 1
* u4  net-_u4-pad1_ net-_u4-pad2_ adc_bridge_1
* u6  qa plot_v1
* u7  qb plot_v1
* u8  qc plot_v1
* u9  qd plot_v1
r4  qd gnd 10k
r3  qc gnd 10k
r2  qb gnd 10k
r1  qa gnd 10k
* u10  net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ net-_u10-pad4_ qa qb qc qd dac_bridge_4
a1 [net-_u2-pad1_ ] [clock ] u2
a2 [net-_u1-pad1_ ] [net-_u1-pad2_ ] u1
a3 [net-_u3-pad1_ ] [net-_u3-pad2_ ] u3
a4 [net-_u4-pad1_ ] [net-_u4-pad2_ ] u4
a5 [net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ net-_u10-pad4_ ] [qa qb qc qd ] u10
* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
.model u1 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
.model u3 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
.model u4 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
* Schematic Name:                             dac_bridge_4, NgSpice Name: dac_bridge
.model u10 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
.tran 0.1e-06 100e-06 0e-00

* Control Statements 
.control
run
print allv > plot_data_v.txt
print alli > plot_data_i.txt
plot v(qd)+6  v(qc)+12 v(qb)+18v(qa)+24 v(clock)
.endc
.end