* c:\users\chaithu\fossee\esim\library\subcircuitlibrary\sn54als29827\sn54als29827.cir

* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u10-pad2_ d_and
* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ net-_u1-pad20_ net-_u1-pad21_ net-_u1-pad22_ port
* u3  net-_u1-pad4_ net-_u10-pad2_ net-_u1-pad14_ tristate_buff
* u5  net-_u1-pad3_ net-_u10-pad2_ net-_u1-pad13_ tristate_buff
* u4  net-_u1-pad6_ net-_u10-pad2_ net-_u1-pad16_ tristate_buff
* u6  net-_u1-pad7_ net-_u10-pad2_ net-_u1-pad22_ tristate_buff
* u7  net-_u1-pad10_ net-_u10-pad2_ net-_u1-pad17_ tristate_buff
* u8  net-_u1-pad8_ net-_u10-pad2_ net-_u1-pad15_ tristate_buff
* u9  net-_u1-pad5_ net-_u10-pad2_ net-_u1-pad18_ tristate_buff
* u10  net-_u1-pad9_ net-_u10-pad2_ net-_u1-pad19_ tristate_buff
* u11  net-_u1-pad11_ net-_u10-pad2_ net-_u1-pad21_ tristate_buff
* u12  net-_u1-pad12_ net-_u10-pad2_ net-_u1-pad20_ tristate_buff
a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u10-pad2_ u2
a2 [net-_u1-pad4_ ] [net-_u10-pad2_ ] [net-_u1-pad14_ ] u3
a3 [net-_u1-pad3_ ] [net-_u10-pad2_ ] [net-_u1-pad13_ ] u5
a4 [net-_u1-pad6_ ] [net-_u10-pad2_ ] [net-_u1-pad16_ ] u4
a5 [net-_u1-pad7_ ] [net-_u10-pad2_ ] [net-_u1-pad22_ ] u6
a6 [net-_u1-pad10_ ] [net-_u10-pad2_ ] [net-_u1-pad17_ ] u7
a7 [net-_u1-pad8_ ] [net-_u10-pad2_ ] [net-_u1-pad15_ ] u8
a8 [net-_u1-pad5_ ] [net-_u10-pad2_ ] [net-_u1-pad18_ ] u9
a9 [net-_u1-pad9_ ] [net-_u10-pad2_ ] [net-_u1-pad19_ ] u10
a10 [net-_u1-pad11_ ] [net-_u10-pad2_ ] [net-_u1-pad21_ ] u11
a11 [net-_u1-pad12_ ] [net-_u10-pad2_ ] [net-_u1-pad20_ ] u12
* Schematic Name:                             d_and, NgSpice Name: d_and
.model u2 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
* Schematic Name:                             tristate_buff, NgSpice Name: tristate_buff
.model u3 tristate_buff(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) 
* Schematic Name:                             tristate_buff, NgSpice Name: tristate_buff
.model u5 tristate_buff(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) 
* Schematic Name:                             tristate_buff, NgSpice Name: tristate_buff
.model u4 tristate_buff(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) 
* Schematic Name:                             tristate_buff, NgSpice Name: tristate_buff
.model u6 tristate_buff(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) 
* Schematic Name:                             tristate_buff, NgSpice Name: tristate_buff
.model u7 tristate_buff(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) 
* Schematic Name:                             tristate_buff, NgSpice Name: tristate_buff
.model u8 tristate_buff(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) 
* Schematic Name:                             tristate_buff, NgSpice Name: tristate_buff
.model u9 tristate_buff(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) 
* Schematic Name:                             tristate_buff, NgSpice Name: tristate_buff
.model u10 tristate_buff(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) 
* Schematic Name:                             tristate_buff, NgSpice Name: tristate_buff
.model u11 tristate_buff(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) 
* Schematic Name:                             tristate_buff, NgSpice Name: tristate_buff
.model u12 tristate_buff(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) 
.tran 0e-00 0e-00 0e-00

* Control Statements 
.control
run
print allv > plot_data_v.txt
print alli > plot_data_i.txt
.endc
.end