* Subcircuit g_origin
.subckt g_origin /w /x /y /z net-_u1-pad5_ 
* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\g_origin\g_origin.cir
.include 4_OR.sub
* u3  /y net-_u3-pad2_ d_inverter
* u4  /z net-_u4-pad2_ d_inverter
x1 net-_u5-pad3_ net-_u6-pad3_ net-_u7-pad3_ net-_u8-pad3_ net-_u1-pad5_ 4_OR
* u2  /x net-_u2-pad2_ d_inverter
* u5  net-_u2-pad2_ /y net-_u5-pad3_ d_and
* u6  /y net-_u4-pad2_ net-_u6-pad3_ d_and
* u7  /x net-_u3-pad2_ net-_u7-pad3_ d_and
* u8  /w net-_u2-pad2_ net-_u8-pad3_ d_and
a1 /y net-_u3-pad2_ u3
a2 /z net-_u4-pad2_ u4
a3 /x net-_u2-pad2_ u2
a4 [net-_u2-pad2_ /y ] net-_u5-pad3_ u5
a5 [/y net-_u4-pad2_ ] net-_u6-pad3_ u6
a6 [/x net-_u3-pad2_ ] net-_u7-pad3_ u7
a7 [/w net-_u2-pad2_ ] net-_u8-pad3_ u8
* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name:                             d_and, NgSpice Name: d_and
.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name:                             d_and, NgSpice Name: d_and
.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name:                             d_and, NgSpice Name: d_and
.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name:                             d_and, NgSpice Name: d_and
.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Control Statements

.ends g_origin