* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\74ac283\74ac283.cir

.include full_adder.sub
x1 net-_u2-pad4_ net-_u2-pad5_ net-_u2-pad6_ net-_u6-pad1_ net-_x1-pad5_ full_adder
x2 net-_u3-pad3_ net-_u3-pad4_ net-_x1-pad5_ net-_u6-pad2_ net-_x2-pad5_ full_adder
x3 net-_u4-pad3_ net-_u4-pad4_ net-_x2-pad5_ net-_u6-pad3_ net-_x3-pad5_ full_adder
x4 net-_u5-pad3_ net-_u5-pad4_ net-_x3-pad5_ net-_u6-pad4_ net-_u6-pad5_ full_adder
* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad4_ net-_u2-pad5_ net-_u2-pad6_ adc_bridge_3
* u3  net-_u1-pad4_ net-_u1-pad5_ net-_u3-pad3_ net-_u3-pad4_ adc_bridge_2
* u4  net-_u1-pad6_ net-_u1-pad7_ net-_u4-pad3_ net-_u4-pad4_ adc_bridge_2
* u5  net-_u1-pad8_ net-_u1-pad9_ net-_u5-pad3_ net-_u5-pad4_ adc_bridge_2
* u6  net-_u6-pad1_ net-_u6-pad2_ net-_u6-pad3_ net-_u6-pad4_ net-_u6-pad5_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ dac_bridge_5
* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ ? ? port
a1 [net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ ] [net-_u2-pad4_ net-_u2-pad5_ net-_u2-pad6_ ] u2
a2 [net-_u1-pad4_ net-_u1-pad5_ ] [net-_u3-pad3_ net-_u3-pad4_ ] u3
a3 [net-_u1-pad6_ net-_u1-pad7_ ] [net-_u4-pad3_ net-_u4-pad4_ ] u4
a4 [net-_u1-pad8_ net-_u1-pad9_ ] [net-_u5-pad3_ net-_u5-pad4_ ] u5
a5 [net-_u6-pad1_ net-_u6-pad2_ net-_u6-pad3_ net-_u6-pad4_ net-_u6-pad5_ ] [net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ ] u6
* Schematic Name:                             adc_bridge_3, NgSpice Name: adc_bridge
.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
* Schematic Name:                             adc_bridge_2, NgSpice Name: adc_bridge
.model u3 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
* Schematic Name:                             adc_bridge_2, NgSpice Name: adc_bridge
.model u4 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
* Schematic Name:                             adc_bridge_2, NgSpice Name: adc_bridge
.model u5 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
* Schematic Name:                             dac_bridge_5, NgSpice Name: dac_bridge
.model u6 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
.tran 0e-00 0e-00 0e-00

* Control Statements 
.control
run
print allv > plot_data_v.txt
print alli > plot_data_i.txt
.endc
.end