* Subcircuit SN74LVC1G139
.subckt SN74LVC1G139 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ 
* c:\users\senba\desktop\fossee\esim\library\subcircuitlibrary\sn74lvc1g139\sn74lvc1g139.cir
* u2  net-_u1-pad1_ net-_u2-pad2_ d_inverter
* u4  net-_u2-pad2_ net-_u10-pad1_ d_inverter
* u8  net-_u10-pad1_ net-_u5-pad2_ net-_u1-pad3_ d_nand
* u3  net-_u1-pad2_ net-_u3-pad2_ d_inverter
* u5  net-_u3-pad2_ net-_u5-pad2_ d_inverter
* u7  net-_u10-pad1_ net-_u11-pad1_ d_inverter
* u9  net-_u11-pad1_ net-_u5-pad2_ net-_u1-pad4_ d_nand
* u6  net-_u5-pad2_ net-_u10-pad2_ d_inverter
* u10  net-_u10-pad1_ net-_u10-pad2_ net-_u1-pad5_ d_nand
* u11  net-_u11-pad1_ net-_u10-pad2_ net-_u1-pad6_ d_nand
a1 net-_u1-pad1_ net-_u2-pad2_ u2
a2 net-_u2-pad2_ net-_u10-pad1_ u4
a3 [net-_u10-pad1_ net-_u5-pad2_ ] net-_u1-pad3_ u8
a4 net-_u1-pad2_ net-_u3-pad2_ u3
a5 net-_u3-pad2_ net-_u5-pad2_ u5
a6 net-_u10-pad1_ net-_u11-pad1_ u7
a7 [net-_u11-pad1_ net-_u5-pad2_ ] net-_u1-pad4_ u9
a8 net-_u5-pad2_ net-_u10-pad2_ u6
a9 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u1-pad5_ u10
a10 [net-_u11-pad1_ net-_u10-pad2_ ] net-_u1-pad6_ u11
* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name:                             d_nand, NgSpice Name: d_nand
.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name:                             d_nand, NgSpice Name: d_nand
.model u9 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name:                             d_nand, NgSpice Name: d_nand
.model u10 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name:                             d_nand, NgSpice Name: d_nand
.model u11 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Control Statements

.ends SN74LVC1G139