* Subcircuit SN74LS47 .subckt SN74LS47 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ ? net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ * c:\users\senba\desktop\fossee\esim\library\subcircuitlibrary\sn74ls47\sn74ls47.cir .include 3_and.sub .include 4_and.sub * u14 net-_u11-pad3_ net-_u13-pad3_ net-_u14-pad3_ d_and * u15 net-_u10-pad1_ net-_u12-pad3_ net-_u15-pad3_ d_and x11 net-_u10-pad3_ net-_u11-pad1_ net-_u12-pad1_ net-_u13-pad1_ net-_u38-pad1_ 4_and * u16 net-_u11-pad3_ net-_u13-pad3_ net-_u16-pad3_ d_and x2 net-_u10-pad3_ net-_u11-pad1_ net-_u12-pad3_ net-_u23-pad1_ 3_and x3 net-_u10-pad1_ net-_u11-pad3_ net-_u12-pad3_ net-_u24-pad1_ 3_and * u17 net-_u12-pad3_ net-_u13-pad3_ net-_u17-pad3_ d_and x4 net-_u10-pad1_ net-_u11-pad3_ net-_u12-pad1_ net-_u29-pad1_ 3_and x5 net-_u10-pad3_ net-_u11-pad1_ net-_u12-pad1_ net-_u26-pad1_ 3_and x6 net-_u10-pad1_ net-_u11-pad1_ net-_u12-pad3_ net-_u9-pad1_ 3_and x7 net-_u10-pad3_ net-_u11-pad3_ net-_u12-pad3_ net-_u27-pad1_ 3_and * u18 net-_u11-pad1_ net-_u12-pad3_ net-_u18-pad3_ d_and * u19 net-_u10-pad3_ net-_u11-pad3_ net-_u19-pad3_ d_and * u20 net-_u11-pad3_ net-_u12-pad1_ net-_u20-pad3_ d_and x8 net-_u10-pad3_ net-_u12-pad1_ net-_u13-pad1_ net-_u35-pad1_ 3_and x9 net-_u10-pad3_ net-_u11-pad3_ net-_u12-pad3_ net-_u36-pad1_ 3_and * u10 net-_u10-pad1_ net-_u1-pad5_ net-_u10-pad3_ d_nand * u11 net-_u11-pad1_ net-_u1-pad5_ net-_u11-pad3_ d_nand * u12 net-_u12-pad1_ net-_u1-pad5_ net-_u12-pad3_ d_nand * u13 net-_u13-pad1_ net-_u1-pad5_ net-_u13-pad3_ d_nand * u2 net-_u1-pad1_ net-_u1-pad6_ net-_u10-pad1_ d_nand * u3 net-_u1-pad2_ net-_u1-pad6_ net-_u11-pad1_ d_nand * u4 net-_u1-pad3_ net-_u1-pad6_ net-_u12-pad1_ d_nand * u5 net-_u1-pad4_ net-_u13-pad1_ d_inverter x10 net-_u11-pad1_ net-_u12-pad1_ net-_u13-pad1_ net-_u1-pad6_ net-_u28-pad1_ 4_and * u49 net-_u1-pad7_ net-_u49-pad2_ d_inverter * u30 net-_u14-pad3_ net-_u30-pad2_ d_inverter * u25 net-_u15-pad3_ net-_u25-pad2_ d_inverter * u38 net-_u38-pad1_ net-_u38-pad2_ d_inverter * u21 net-_u17-pad3_ net-_u21-pad2_ d_inverter * u29 net-_u29-pad1_ net-_u29-pad2_ d_inverter * u26 net-_u26-pad1_ net-_u26-pad2_ d_inverter * u9 net-_u9-pad1_ net-_u9-pad2_ d_inverter * u27 net-_u27-pad1_ net-_u27-pad2_ d_inverter * u37 net-_u10-pad3_ net-_u37-pad2_ d_inverter * u31 net-_u18-pad3_ net-_u31-pad2_ d_inverter * u33 net-_u19-pad3_ net-_u33-pad2_ d_inverter * u34 net-_u20-pad3_ net-_u34-pad2_ d_inverter * u35 net-_u35-pad1_ net-_u35-pad2_ d_inverter * u36 net-_u36-pad1_ net-_u36-pad2_ d_inverter * u28 net-_u28-pad1_ net-_u28-pad2_ d_inverter x12 net-_u30-pad2_ net-_u25-pad2_ net-_u38-pad2_ net-_u1-pad8_ 3_and x13 net-_u22-pad2_ net-_u23-pad2_ net-_u24-pad2_ ? 3_and x14 net-_u26-pad2_ net-_u9-pad2_ net-_u27-pad2_ net-_u1-pad11_ 3_and * u41 net-_u37-pad2_ net-_u31-pad2_ net-_u1-pad12_ d_and x15 net-_u33-pad2_ net-_u34-pad2_ net-_u35-pad2_ net-_u1-pad13_ 3_and * u39 net-_u36-pad2_ net-_u28-pad2_ net-_u1-pad14_ d_and * u22 net-_u16-pad3_ net-_u22-pad2_ d_inverter * u23 net-_u23-pad1_ net-_u23-pad2_ d_inverter * u24 net-_u24-pad1_ net-_u24-pad2_ d_inverter * u40 net-_u21-pad2_ net-_u29-pad2_ net-_u1-pad10_ d_and x1 net-_u1-pad6_ net-_u49-pad2_ net-_u13-pad1_ net-_u12-pad1_ net-_u6-pad1_ 4_and * u7 net-_u12-pad3_ net-_u10-pad1_ net-_u6-pad2_ d_and * u6 net-_u6-pad1_ net-_u6-pad2_ net-_u1-pad5_ d_nand a1 [net-_u11-pad3_ net-_u13-pad3_ ] net-_u14-pad3_ u14 a2 [net-_u10-pad1_ net-_u12-pad3_ ] net-_u15-pad3_ u15 a3 [net-_u11-pad3_ net-_u13-pad3_ ] net-_u16-pad3_ u16 a4 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u17-pad3_ u17 a5 [net-_u11-pad1_ net-_u12-pad3_ ] net-_u18-pad3_ u18 a6 [net-_u10-pad3_ net-_u11-pad3_ ] net-_u19-pad3_ u19 a7 [net-_u11-pad3_ net-_u12-pad1_ ] net-_u20-pad3_ u20 a8 [net-_u10-pad1_ net-_u1-pad5_ ] net-_u10-pad3_ u10 a9 [net-_u11-pad1_ net-_u1-pad5_ ] net-_u11-pad3_ u11 a10 [net-_u12-pad1_ net-_u1-pad5_ ] net-_u12-pad3_ u12 a11 [net-_u13-pad1_ net-_u1-pad5_ ] net-_u13-pad3_ u13 a12 [net-_u1-pad1_ net-_u1-pad6_ ] net-_u10-pad1_ u2 a13 [net-_u1-pad2_ net-_u1-pad6_ ] net-_u11-pad1_ u3 a14 [net-_u1-pad3_ net-_u1-pad6_ ] net-_u12-pad1_ u4 a15 net-_u1-pad4_ net-_u13-pad1_ u5 a16 net-_u1-pad7_ net-_u49-pad2_ u49 a17 net-_u14-pad3_ net-_u30-pad2_ u30 a18 net-_u15-pad3_ net-_u25-pad2_ u25 a19 net-_u38-pad1_ net-_u38-pad2_ u38 a20 net-_u17-pad3_ net-_u21-pad2_ u21 a21 net-_u29-pad1_ net-_u29-pad2_ u29 a22 net-_u26-pad1_ net-_u26-pad2_ u26 a23 net-_u9-pad1_ net-_u9-pad2_ u9 a24 net-_u27-pad1_ net-_u27-pad2_ u27 a25 net-_u10-pad3_ net-_u37-pad2_ u37 a26 net-_u18-pad3_ net-_u31-pad2_ u31 a27 net-_u19-pad3_ net-_u33-pad2_ u33 a28 net-_u20-pad3_ net-_u34-pad2_ u34 a29 net-_u35-pad1_ net-_u35-pad2_ u35 a30 net-_u36-pad1_ net-_u36-pad2_ u36 a31 net-_u28-pad1_ net-_u28-pad2_ u28 a32 [net-_u37-pad2_ net-_u31-pad2_ ] net-_u1-pad12_ u41 a33 [net-_u36-pad2_ net-_u28-pad2_ ] net-_u1-pad14_ u39 a34 net-_u16-pad3_ net-_u22-pad2_ u22 a35 net-_u23-pad1_ net-_u23-pad2_ u23 a36 net-_u24-pad1_ net-_u24-pad2_ u24 a37 [net-_u21-pad2_ net-_u29-pad2_ ] net-_u1-pad10_ u40 a38 [net-_u12-pad3_ net-_u10-pad1_ ] net-_u6-pad2_ u7 a39 [net-_u6-pad1_ net-_u6-pad2_ ] net-_u1-pad5_ u6 * Schematic Name: d_and, NgSpice Name: d_and .model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_and, NgSpice Name: d_and .model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_and, NgSpice Name: d_and .model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_and, NgSpice Name: d_and .model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_and, NgSpice Name: d_and .model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_and, NgSpice Name: d_and .model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_and, NgSpice Name: d_and .model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_nand, NgSpice Name: d_nand .model u10 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_nand, NgSpice Name: d_nand .model u11 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_nand, NgSpice Name: d_nand .model u12 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_nand, NgSpice Name: d_nand .model u13 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_nand, NgSpice Name: d_nand .model u2 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_nand, NgSpice Name: d_nand .model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_nand, NgSpice Name: d_nand .model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u49 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u38 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u37 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u33 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u35 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u36 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_and, NgSpice Name: d_and .model u41 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_and, NgSpice Name: d_and .model u39 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_and, NgSpice Name: d_and .model u40 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_and, NgSpice Name: d_and .model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_nand, NgSpice Name: d_nand .model u6 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Control Statements .ends SN74LS47