* Subcircuit SN74ALS280 .subckt SN74ALS280 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ * c:\fossee\esim\library\subcircuitlibrary\sn74als280\sn74als280.cir .include 4_and.sub .include 4_OR.sub .include 3_and.sub * u13 net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_and * u14 net-_u13-pad1_ net-_u14-pad2_ net-_u14-pad3_ d_and * u15 net-_u14-pad2_ net-_u13-pad2_ net-_u15-pad3_ d_and x19 net-_u1-pad3_ net-_u1-pad2_ ? net-_u31-pad1_ 3_and * u22 net-_u22-pad1_ net-_u13-pad3_ net-_u22-pad3_ d_nand * u23 net-_u23-pad1_ net-_u14-pad3_ net-_u23-pad3_ d_nand * u24 net-_u24-pad1_ net-_u15-pad3_ net-_u24-pad3_ d_nand x22 net-_u31-pad2_ net-_u22-pad3_ net-_u23-pad3_ net-_u24-pad3_ net-_u34-pad1_ 4_and * u31 net-_u31-pad1_ net-_u31-pad2_ d_inverter * u34 net-_u34-pad1_ net-_u34-pad2_ d_inverter * u35 net-_u35-pad1_ net-_u35-pad2_ d_inverter * u36 net-_u36-pad1_ net-_u36-pad2_ d_inverter x29 net-_u34-pad2_ net-_u35-pad1_ net-_u36-pad1_ net-_x29-pad4_ 3_and x30 net-_u34-pad1_ net-_u35-pad2_ net-_u36-pad1_ net-_x30-pad4_ 3_and x31 net-_u34-pad1_ net-_u36-pad2_ net-_u35-pad1_ net-_x31-pad4_ 3_and x32 net-_u34-pad2_ net-_u36-pad2_ net-_u35-pad2_ net-_x32-pad4_ 3_and x34 net-_x29-pad4_ net-_x30-pad4_ net-_x31-pad4_ net-_x32-pad4_ net-_u38-pad1_ 4_OR * u38 net-_u38-pad1_ net-_u1-pad10_ d_inverter x25 net-_u34-pad1_ net-_u36-pad2_ net-_u35-pad2_ net-_x25-pad4_ 3_and x26 net-_u34-pad2_ net-_u36-pad2_ net-_u35-pad1_ net-_x26-pad4_ 3_and x27 net-_u34-pad2_ net-_u35-pad2_ net-_u36-pad1_ net-_x27-pad4_ 3_and x28 net-_u34-pad1_ net-_u35-pad1_ net-_u36-pad1_ net-_x28-pad4_ 3_and x33 net-_x25-pad4_ net-_x26-pad4_ net-_x27-pad4_ net-_x28-pad4_ net-_u37-pad1_ 4_OR * u37 net-_u37-pad1_ net-_u1-pad11_ d_inverter * u17 net-_u1-pad2_ net-_u13-pad2_ d_inverter * u43 net-_u14-pad2_ net-_u22-pad1_ d_inverter * u16 net-_u1-pad1_ net-_u14-pad2_ d_inverter * u44 net-_u13-pad2_ net-_u23-pad1_ d_inverter * u18 net-_u1-pad3_ net-_u13-pad1_ d_inverter * u45 net-_u13-pad1_ net-_u24-pad1_ d_inverter * u28 net-_u21-pad2_ net-_u20-pad2_ net-_u28-pad3_ d_and * u29 net-_u21-pad2_ net-_u19-pad2_ net-_u29-pad3_ d_and * u30 net-_u19-pad2_ net-_u20-pad2_ net-_u30-pad3_ d_and x1 net-_u1-pad6_ net-_u1-pad5_ ? net-_u58-pad1_ 3_and * u52 net-_u46-pad2_ net-_u28-pad3_ net-_u52-pad3_ d_nand * u53 net-_u47-pad2_ net-_u29-pad3_ net-_u53-pad3_ d_nand * u54 net-_u48-pad2_ net-_u30-pad3_ net-_u54-pad3_ d_nand x3 net-_u58-pad2_ net-_u52-pad3_ net-_u53-pad3_ net-_u54-pad3_ net-_u35-pad1_ 4_and * u58 net-_u58-pad1_ net-_u58-pad2_ d_inverter * u20 net-_u1-pad5_ net-_u20-pad2_ d_inverter * u46 net-_u19-pad2_ net-_u46-pad2_ d_inverter * u19 net-_u1-pad4_ net-_u19-pad2_ d_inverter * u47 net-_u20-pad2_ net-_u47-pad2_ d_inverter * u21 net-_u1-pad6_ net-_u21-pad2_ d_inverter * u48 net-_u21-pad2_ net-_u48-pad2_ d_inverter * u32 net-_u27-pad2_ net-_u26-pad2_ net-_u32-pad3_ d_and * u33 net-_u27-pad2_ net-_u25-pad2_ net-_u33-pad3_ d_and * u42 net-_u25-pad2_ net-_u26-pad2_ net-_u42-pad3_ d_and x2 net-_u1-pad9_ net-_u1-pad8_ ? net-_u59-pad1_ 3_and * u55 net-_u49-pad2_ net-_u32-pad3_ net-_u55-pad3_ d_nand * u56 net-_u50-pad2_ net-_u33-pad3_ net-_u56-pad3_ d_nand * u57 net-_u51-pad2_ net-_u42-pad3_ net-_u57-pad3_ d_nand x4 net-_u59-pad2_ net-_u55-pad3_ net-_u56-pad3_ net-_u57-pad3_ net-_u36-pad1_ 4_and * u59 net-_u59-pad1_ net-_u59-pad2_ d_inverter * u26 net-_u1-pad8_ net-_u26-pad2_ d_inverter * u49 net-_u25-pad2_ net-_u49-pad2_ d_inverter * u25 net-_u1-pad7_ net-_u25-pad2_ d_inverter * u50 net-_u26-pad2_ net-_u50-pad2_ d_inverter * u27 net-_u1-pad9_ net-_u27-pad2_ d_inverter * u51 net-_u27-pad2_ net-_u51-pad2_ d_inverter a1 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13 a2 [net-_u13-pad1_ net-_u14-pad2_ ] net-_u14-pad3_ u14 a3 [net-_u14-pad2_ net-_u13-pad2_ ] net-_u15-pad3_ u15 a4 [net-_u22-pad1_ net-_u13-pad3_ ] net-_u22-pad3_ u22 a5 [net-_u23-pad1_ net-_u14-pad3_ ] net-_u23-pad3_ u23 a6 [net-_u24-pad1_ net-_u15-pad3_ ] net-_u24-pad3_ u24 a7 net-_u31-pad1_ net-_u31-pad2_ u31 a8 net-_u34-pad1_ net-_u34-pad2_ u34 a9 net-_u35-pad1_ net-_u35-pad2_ u35 a10 net-_u36-pad1_ net-_u36-pad2_ u36 a11 net-_u38-pad1_ net-_u1-pad10_ u38 a12 net-_u37-pad1_ net-_u1-pad11_ u37 a13 net-_u1-pad2_ net-_u13-pad2_ u17 a14 net-_u14-pad2_ net-_u22-pad1_ u43 a15 net-_u1-pad1_ net-_u14-pad2_ u16 a16 net-_u13-pad2_ net-_u23-pad1_ u44 a17 net-_u1-pad3_ net-_u13-pad1_ u18 a18 net-_u13-pad1_ net-_u24-pad1_ u45 a19 [net-_u21-pad2_ net-_u20-pad2_ ] net-_u28-pad3_ u28 a20 [net-_u21-pad2_ net-_u19-pad2_ ] net-_u29-pad3_ u29 a21 [net-_u19-pad2_ net-_u20-pad2_ ] net-_u30-pad3_ u30 a22 [net-_u46-pad2_ net-_u28-pad3_ ] net-_u52-pad3_ u52 a23 [net-_u47-pad2_ net-_u29-pad3_ ] net-_u53-pad3_ u53 a24 [net-_u48-pad2_ net-_u30-pad3_ ] net-_u54-pad3_ u54 a25 net-_u58-pad1_ net-_u58-pad2_ u58 a26 net-_u1-pad5_ net-_u20-pad2_ u20 a27 net-_u19-pad2_ net-_u46-pad2_ u46 a28 net-_u1-pad4_ net-_u19-pad2_ u19 a29 net-_u20-pad2_ net-_u47-pad2_ u47 a30 net-_u1-pad6_ net-_u21-pad2_ u21 a31 net-_u21-pad2_ net-_u48-pad2_ u48 a32 [net-_u27-pad2_ net-_u26-pad2_ ] net-_u32-pad3_ u32 a33 [net-_u27-pad2_ net-_u25-pad2_ ] net-_u33-pad3_ u33 a34 [net-_u25-pad2_ net-_u26-pad2_ ] net-_u42-pad3_ u42 a35 [net-_u49-pad2_ net-_u32-pad3_ ] net-_u55-pad3_ u55 a36 [net-_u50-pad2_ net-_u33-pad3_ ] net-_u56-pad3_ u56 a37 [net-_u51-pad2_ net-_u42-pad3_ ] net-_u57-pad3_ u57 a38 net-_u59-pad1_ net-_u59-pad2_ u59 a39 net-_u1-pad8_ net-_u26-pad2_ u26 a40 net-_u25-pad2_ net-_u49-pad2_ u49 a41 net-_u1-pad7_ net-_u25-pad2_ u25 a42 net-_u26-pad2_ net-_u50-pad2_ u50 a43 net-_u1-pad9_ net-_u27-pad2_ u27 a44 net-_u27-pad2_ net-_u51-pad2_ u51 * Schematic Name: d_and, NgSpice Name: d_and .model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_and, NgSpice Name: d_and .model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_and, NgSpice Name: d_and .model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_nand, NgSpice Name: d_nand .model u22 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_nand, NgSpice Name: d_nand .model u23 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_nand, NgSpice Name: d_nand .model u24 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u35 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u36 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u38 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u37 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u43 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u44 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u45 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_and, NgSpice Name: d_and .model u28 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_and, NgSpice Name: d_and .model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_and, NgSpice Name: d_and .model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_nand, NgSpice Name: d_nand .model u52 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_nand, NgSpice Name: d_nand .model u53 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_nand, NgSpice Name: d_nand .model u54 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u58 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u46 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u47 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u48 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_and, NgSpice Name: d_and .model u32 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_and, NgSpice Name: d_and .model u33 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_and, NgSpice Name: d_and .model u42 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_nand, NgSpice Name: d_nand .model u55 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_nand, NgSpice Name: d_nand .model u56 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_nand, NgSpice Name: d_nand .model u57 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u59 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u49 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u50 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u51 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Control Statements .ends SN74ALS280