* Subcircuit SN74120 .subckt SN74120 /m_1 /s1_bar_1 /s2_bar_1 /r_bar_1 /c_1 /y_1 /y_bar_1 ? /y_bar_2 /y_2 /c_2 /r_bar_2 /s1_bar_2 /s2_bar_2 ? /m_2 * c:\fossee\esim\library\subcircuitlibrary\sn74120\sn74120.cir .include 3_and.sub * u2 /r_bar_1 net-_u2-pad2_ d_inverter * u3 net-_u11-pad3_ net-_u3-pad2_ d_inverter * u4 net-_u4-pad1_ net-_u4-pad2_ d_inverter * u5 /s1_bar_1 net-_u5-pad2_ d_inverter * u6 /s2_bar_1 net-_u11-pad2_ d_inverter * u7 /c_1 net-_u7-pad2_ d_inverter * u8 net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad1_ d_or * u9 net-_u4-pad2_ net-_u5-pad2_ net-_u11-pad1_ d_or * u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_or * u10 net-_u10-pad1_ /c_1 /y_bar_1 d_nand * u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter * u13 net-_u12-pad2_ net-_u13-pad2_ d_inverter * u16 /y_bar_1 net-_u16-pad2_ d_inverter * u17 net-_u17-pad1_ net-_u17-pad2_ net-_u15-pad1_ d_or * u15 net-_u15-pad1_ net-_u14-pad2_ net-_u10-pad1_ d_or * u19 net-_u16-pad2_ net-_u13-pad2_ net-_u19-pad3_ d_or * u18 /y_bar_1 /y_1 d_inverter x1 net-_u7-pad2_ net-_u11-pad3_ net-_u12-pad2_ net-_u17-pad1_ 3_and x2 net-_u11-pad3_ net-_u12-pad2_ net-_u10-pad1_ net-_u17-pad2_ 3_and x3 net-_u11-pad3_ /m_1 net-_u19-pad3_ net-_u12-pad1_ 3_and * u14 /y_bar_1 net-_u14-pad2_ d_inverter * u20 /r_bar_2 net-_u20-pad2_ d_inverter * u21 net-_u21-pad1_ net-_u21-pad2_ d_inverter * u22 net-_u22-pad1_ net-_u22-pad2_ d_inverter * u23 /s1_bar_2 net-_u23-pad2_ d_inverter * u24 /s2_bar_2 net-_u24-pad2_ d_inverter * u25 /c_2 net-_u25-pad2_ d_inverter * u26 net-_u20-pad2_ net-_u21-pad2_ net-_u22-pad1_ d_or * u27 net-_u22-pad2_ net-_u23-pad2_ net-_u27-pad3_ d_or * u29 net-_u27-pad3_ net-_u24-pad2_ net-_u21-pad1_ d_or * u28 net-_u28-pad1_ /c_2 /y_bar_2 d_nand x4 net-_u25-pad2_ net-_u21-pad1_ net-_u30-pad2_ net-_u35-pad1_ 3_and x5 net-_u21-pad1_ net-_u30-pad2_ net-_u28-pad1_ net-_u35-pad2_ 3_and x6 net-_u21-pad1_ /m_2 net-_u36-pad3_ net-_u30-pad1_ 3_and * u30 net-_u30-pad1_ net-_u30-pad2_ d_inverter * u31 net-_u30-pad2_ net-_u31-pad2_ d_inverter * u34 /y_bar_2 net-_u34-pad2_ d_inverter * u35 net-_u35-pad1_ net-_u35-pad2_ net-_u33-pad1_ d_or * u33 net-_u33-pad1_ net-_u32-pad2_ net-_u28-pad1_ d_or * u37 /y_bar_2 /y_2 d_inverter * u32 /y_bar_2 net-_u32-pad2_ d_inverter * u36 net-_u34-pad2_ net-_u31-pad2_ net-_u36-pad3_ d_or a1 /r_bar_1 net-_u2-pad2_ u2 a2 net-_u11-pad3_ net-_u3-pad2_ u3 a3 net-_u4-pad1_ net-_u4-pad2_ u4 a4 /s1_bar_1 net-_u5-pad2_ u5 a5 /s2_bar_1 net-_u11-pad2_ u6 a6 /c_1 net-_u7-pad2_ u7 a7 [net-_u2-pad2_ net-_u3-pad2_ ] net-_u4-pad1_ u8 a8 [net-_u4-pad2_ net-_u5-pad2_ ] net-_u11-pad1_ u9 a9 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11 a10 [net-_u10-pad1_ /c_1 ] /y_bar_1 u10 a11 net-_u12-pad1_ net-_u12-pad2_ u12 a12 net-_u12-pad2_ net-_u13-pad2_ u13 a13 /y_bar_1 net-_u16-pad2_ u16 a14 [net-_u17-pad1_ net-_u17-pad2_ ] net-_u15-pad1_ u17 a15 [net-_u15-pad1_ net-_u14-pad2_ ] net-_u10-pad1_ u15 a16 [net-_u16-pad2_ net-_u13-pad2_ ] net-_u19-pad3_ u19 a17 /y_bar_1 /y_1 u18 a18 /y_bar_1 net-_u14-pad2_ u14 a19 /r_bar_2 net-_u20-pad2_ u20 a20 net-_u21-pad1_ net-_u21-pad2_ u21 a21 net-_u22-pad1_ net-_u22-pad2_ u22 a22 /s1_bar_2 net-_u23-pad2_ u23 a23 /s2_bar_2 net-_u24-pad2_ u24 a24 /c_2 net-_u25-pad2_ u25 a25 [net-_u20-pad2_ net-_u21-pad2_ ] net-_u22-pad1_ u26 a26 [net-_u22-pad2_ net-_u23-pad2_ ] net-_u27-pad3_ u27 a27 [net-_u27-pad3_ net-_u24-pad2_ ] net-_u21-pad1_ u29 a28 [net-_u28-pad1_ /c_2 ] /y_bar_2 u28 a29 net-_u30-pad1_ net-_u30-pad2_ u30 a30 net-_u30-pad2_ net-_u31-pad2_ u31 a31 /y_bar_2 net-_u34-pad2_ u34 a32 [net-_u35-pad1_ net-_u35-pad2_ ] net-_u33-pad1_ u35 a33 [net-_u33-pad1_ net-_u32-pad2_ ] net-_u28-pad1_ u33 a34 /y_bar_2 /y_2 u37 a35 /y_bar_2 net-_u32-pad2_ u32 a36 [net-_u34-pad2_ net-_u31-pad2_ ] net-_u36-pad3_ u36 * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_or, NgSpice Name: d_or .model u8 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_or, NgSpice Name: d_or .model u9 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_or, NgSpice Name: d_or .model u11 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_nand, NgSpice Name: d_nand .model u10 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_or, NgSpice Name: d_or .model u17 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_or, NgSpice Name: d_or .model u15 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_or, NgSpice Name: d_or .model u19 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_or, NgSpice Name: d_or .model u26 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_or, NgSpice Name: d_or .model u27 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_or, NgSpice Name: d_or .model u29 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_nand, NgSpice Name: d_nand .model u28 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_or, NgSpice Name: d_or .model u35 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_or, NgSpice Name: d_or .model u33 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u37 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u32 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_or, NgSpice Name: d_or .model u36 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Control Statements .ends SN74120