* c:\users\chaithu\fossee\esim\library\subcircuitlibrary\sn54hc164\sn54hc164.cir

* u4  net-_u1-pad2_ net-_u1-pad1_ net-_u3-pad1_ d_and
* u2  net-_u1-pad3_ net-_u10-pad2_ d_buffer
* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ port
* u7  net-_u1-pad5_ net-_u10-pad2_ net-_u10-pad3_ net-_u1-pad7_ dff_rst
* u3  net-_u3-pad1_ net-_u10-pad2_ net-_u10-pad3_ net-_u1-pad5_ dff_rst
* u9  net-_u1-pad7_ net-_u10-pad2_ net-_u10-pad3_ net-_u1-pad9_ dff_rst
* u11  net-_u1-pad9_ net-_u10-pad2_ net-_u10-pad3_ net-_u1-pad11_ dff_rst
* u5  net-_u1-pad11_ net-_u10-pad2_ net-_u10-pad3_ net-_u1-pad6_ dff_rst
* u8  net-_u1-pad6_ net-_u10-pad2_ net-_u10-pad3_ net-_u1-pad8_ dff_rst
* u10  net-_u1-pad8_ net-_u10-pad2_ net-_u10-pad3_ net-_u1-pad10_ dff_rst
* u12  net-_u1-pad10_ net-_u10-pad2_ net-_u10-pad3_ net-_u1-pad12_ dff_rst
* u6  net-_u1-pad4_ net-_u10-pad3_ d_inverter
a1 [net-_u1-pad2_ net-_u1-pad1_ ] net-_u3-pad1_ u4
a2 net-_u1-pad3_ net-_u10-pad2_ u2
a3 [net-_u1-pad5_ ] [net-_u10-pad2_ ] [net-_u10-pad3_ ] [net-_u1-pad7_ ] u7
a4 [net-_u3-pad1_ ] [net-_u10-pad2_ ] [net-_u10-pad3_ ] [net-_u1-pad5_ ] u3
a5 [net-_u1-pad7_ ] [net-_u10-pad2_ ] [net-_u10-pad3_ ] [net-_u1-pad9_ ] u9
a6 [net-_u1-pad9_ ] [net-_u10-pad2_ ] [net-_u10-pad3_ ] [net-_u1-pad11_ ] u11
a7 [net-_u1-pad11_ ] [net-_u10-pad2_ ] [net-_u10-pad3_ ] [net-_u1-pad6_ ] u5
a8 [net-_u1-pad6_ ] [net-_u10-pad2_ ] [net-_u10-pad3_ ] [net-_u1-pad8_ ] u8
a9 [net-_u1-pad8_ ] [net-_u10-pad2_ ] [net-_u10-pad3_ ] [net-_u1-pad10_ ] u10
a10 [net-_u1-pad10_ ] [net-_u10-pad2_ ] [net-_u10-pad3_ ] [net-_u1-pad12_ ] u12
a11 net-_u1-pad4_ net-_u10-pad3_ u6
* Schematic Name:                             d_and, NgSpice Name: d_and
.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
* Schematic Name:                             d_buffer, NgSpice Name: d_buffer
.model u2 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
* Schematic Name:                             dff_rst, NgSpice Name: dff_rst
.model u7 dff_rst(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) 
* Schematic Name:                             dff_rst, NgSpice Name: dff_rst
.model u3 dff_rst(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) 
* Schematic Name:                             dff_rst, NgSpice Name: dff_rst
.model u9 dff_rst(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) 
* Schematic Name:                             dff_rst, NgSpice Name: dff_rst
.model u11 dff_rst(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) 
* Schematic Name:                             dff_rst, NgSpice Name: dff_rst
.model u5 dff_rst(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) 
* Schematic Name:                             dff_rst, NgSpice Name: dff_rst
.model u8 dff_rst(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) 
* Schematic Name:                             dff_rst, NgSpice Name: dff_rst
.model u10 dff_rst(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) 
* Schematic Name:                             dff_rst, NgSpice Name: dff_rst
.model u12 dff_rst(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) 
* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
.tran 0e-00 0e-00 0e-00

* Control Statements 
.control
run
print allv > plot_data_v.txt
print alli > plot_data_i.txt
.endc
.end