* /home/kamalesh/downloads/esim-2.3/library/subcircuitlibrary/sn54155/sn54155.cir

.include 3_and.sub
* u6  net-_u1-pad2_ net-_u11-pad1_ d_inverter
* u5  net-_u2-pad2_ net-_u11-pad2_ d_inverter
* u3  net-_u1-pad3_ net-_u3-pad2_ d_inverter
* u12  net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_and
* u9  net-_u3-pad2_ net-_u9-pad2_ d_inverter
x3 net-_u3-pad2_ net-_u10-pad1_ net-_u11-pad3_ net-_u15-pad1_ 3_and
* u8  net-_u1-pad15_ net-_u12-pad1_ d_inverter
* u7  net-_u1-pad14_ net-_u12-pad2_ d_inverter
* u2  net-_u1-pad1_ net-_u2-pad2_ d_inverter
* u11  net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_and
* u4  net-_u1-pad13_ net-_u10-pad1_ d_inverter
* u10  net-_u10-pad1_ net-_u10-pad2_ d_inverter
* u15  net-_u15-pad1_ net-_u1-pad7_ d_inverter
x1 net-_u3-pad2_ net-_u10-pad2_ net-_u11-pad3_ net-_u13-pad1_ 3_and
* u13  net-_u13-pad1_ net-_u1-pad6_ d_inverter
x7 net-_u9-pad2_ net-_u10-pad1_ net-_u11-pad3_ net-_u19-pad1_ 3_and
* u19  net-_u19-pad1_ net-_u1-pad5_ d_inverter
x4 net-_u9-pad2_ net-_u10-pad2_ net-_u11-pad3_ net-_u16-pad1_ 3_and
* u16  net-_u16-pad1_ net-_u1-pad4_ d_inverter
x5 net-_u3-pad2_ net-_u10-pad1_ net-_u12-pad3_ net-_u17-pad1_ 3_and
* u17  net-_u17-pad1_ net-_u1-pad9_ d_inverter
x2 net-_u3-pad2_ net-_u10-pad2_ net-_u12-pad3_ net-_u14-pad1_ 3_and
* u14  net-_u14-pad1_ net-_u1-pad10_ d_inverter
x8 net-_u9-pad2_ net-_u10-pad1_ net-_u12-pad3_ net-_u20-pad1_ 3_and
* u20  net-_u20-pad1_ net-_u1-pad11_ d_inverter
x6 net-_u9-pad2_ net-_u10-pad2_ net-_u12-pad3_ net-_u18-pad1_ 3_and
* u18  net-_u18-pad1_ net-_u1-pad12_ d_inverter
* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? port
a1 net-_u1-pad2_ net-_u11-pad1_ u6
a2 net-_u2-pad2_ net-_u11-pad2_ u5
a3 net-_u1-pad3_ net-_u3-pad2_ u3
a4 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12
a5 net-_u3-pad2_ net-_u9-pad2_ u9
a6 net-_u1-pad15_ net-_u12-pad1_ u8
a7 net-_u1-pad14_ net-_u12-pad2_ u7
a8 net-_u1-pad1_ net-_u2-pad2_ u2
a9 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11
a10 net-_u1-pad13_ net-_u10-pad1_ u4
a11 net-_u10-pad1_ net-_u10-pad2_ u10
a12 net-_u15-pad1_ net-_u1-pad7_ u15
a13 net-_u13-pad1_ net-_u1-pad6_ u13
a14 net-_u19-pad1_ net-_u1-pad5_ u19
a15 net-_u16-pad1_ net-_u1-pad4_ u16
a16 net-_u17-pad1_ net-_u1-pad9_ u17
a17 net-_u14-pad1_ net-_u1-pad10_ u14
a18 net-_u20-pad1_ net-_u1-pad11_ u20
a19 net-_u18-pad1_ net-_u1-pad12_ u18
* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
* Schematic Name:                             d_and, NgSpice Name: d_and
.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
* Schematic Name:                             d_and, NgSpice Name: d_and
.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
.tran 0e-00 0e-00 0e-00

* Control Statements 
.control
run
print allv > plot_data_v.txt
print alli > plot_data_i.txt
.endc
.end