* c:\fossee\esim\library\subcircuitlibrary\hcc4076b\hcc4076b.cir

* u4  net-_u1-pad1_ net-_u1-pad2_ net-_u29-pad2_ d_nand
* u6  net-_u10-pad2_ net-_u11-pad2_ d_inverter
* u7  net-_u21-pad5_ net-_u11-pad2_ net-_u17-pad1_ d_and
* u8  net-_u1-pad8_ net-_u10-pad2_ net-_u17-pad2_ d_and
* u17  net-_u17-pad1_ net-_u17-pad2_ net-_u17-pad3_ d_or
* u21  net-_u17-pad3_ net-_u2-pad2_ net-_u1-pad6_ net-_u21-pad4_ net-_u21-pad5_ net-_u21-pad6_ d_dff
* u29  net-_u21-pad6_ net-_u29-pad2_ net-_u1-pad12_ d_tristate
* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ port
* u9  net-_u22-pad5_ net-_u11-pad2_ net-_u18-pad1_ d_and
* u10  net-_u1-pad9_ net-_u10-pad2_ net-_u10-pad3_ d_and
* u18  net-_u18-pad1_ net-_u10-pad3_ net-_u18-pad3_ d_or
* u22  net-_u18-pad3_ net-_u2-pad2_ net-_u1-pad6_ net-_u21-pad4_ net-_u22-pad5_ net-_u22-pad6_ d_dff
* u30  net-_u22-pad6_ net-_u29-pad2_ net-_u1-pad13_ d_tristate
* u3  net-_u1-pad3_ net-_u1-pad4_ net-_u10-pad2_ d_nand
* u2  net-_u1-pad7_ net-_u2-pad2_ d_inverter
* u11  net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_and
* u12  net-_u1-pad10_ net-_u10-pad2_ net-_u12-pad3_ d_and
* u19  net-_u11-pad3_ net-_u12-pad3_ net-_u19-pad3_ d_or
* u23  net-_u19-pad3_ net-_u2-pad2_ net-_u1-pad6_ net-_u21-pad4_ net-_u11-pad1_ net-_u23-pad6_ d_dff
* u31  net-_u23-pad6_ net-_u29-pad2_ net-_u1-pad14_ d_tristate
* u13  net-_u13-pad1_ net-_u11-pad2_ net-_u13-pad3_ d_and
* u15  net-_u1-pad11_ net-_u10-pad2_ net-_u15-pad3_ d_and
* u20  net-_u13-pad3_ net-_u15-pad3_ net-_u20-pad3_ d_or
* u24  net-_u20-pad3_ net-_u2-pad2_ net-_u1-pad6_ net-_u21-pad4_ net-_u13-pad1_ net-_u24-pad6_ d_dff
* u32  net-_u24-pad6_ net-_u29-pad2_ net-_u1-pad15_ d_tristate
* u5  net-_u1-pad5_ net-_u21-pad4_ d_inverter
a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u29-pad2_ u4
a2 net-_u10-pad2_ net-_u11-pad2_ u6
a3 [net-_u21-pad5_ net-_u11-pad2_ ] net-_u17-pad1_ u7
a4 [net-_u1-pad8_ net-_u10-pad2_ ] net-_u17-pad2_ u8
a5 [net-_u17-pad1_ net-_u17-pad2_ ] net-_u17-pad3_ u17
a6 net-_u17-pad3_ net-_u2-pad2_ net-_u1-pad6_ net-_u21-pad4_ net-_u21-pad5_ net-_u21-pad6_ u21
a7 net-_u21-pad6_ net-_u29-pad2_ net-_u1-pad12_ u29
a8 [net-_u22-pad5_ net-_u11-pad2_ ] net-_u18-pad1_ u9
a9 [net-_u1-pad9_ net-_u10-pad2_ ] net-_u10-pad3_ u10
a10 [net-_u18-pad1_ net-_u10-pad3_ ] net-_u18-pad3_ u18
a11 net-_u18-pad3_ net-_u2-pad2_ net-_u1-pad6_ net-_u21-pad4_ net-_u22-pad5_ net-_u22-pad6_ u22
a12 net-_u22-pad6_ net-_u29-pad2_ net-_u1-pad13_ u30
a13 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u10-pad2_ u3
a14 net-_u1-pad7_ net-_u2-pad2_ u2
a15 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11
a16 [net-_u1-pad10_ net-_u10-pad2_ ] net-_u12-pad3_ u12
a17 [net-_u11-pad3_ net-_u12-pad3_ ] net-_u19-pad3_ u19
a18 net-_u19-pad3_ net-_u2-pad2_ net-_u1-pad6_ net-_u21-pad4_ net-_u11-pad1_ net-_u23-pad6_ u23
a19 net-_u23-pad6_ net-_u29-pad2_ net-_u1-pad14_ u31
a20 [net-_u13-pad1_ net-_u11-pad2_ ] net-_u13-pad3_ u13
a21 [net-_u1-pad11_ net-_u10-pad2_ ] net-_u15-pad3_ u15
a22 [net-_u13-pad3_ net-_u15-pad3_ ] net-_u20-pad3_ u20
a23 net-_u20-pad3_ net-_u2-pad2_ net-_u1-pad6_ net-_u21-pad4_ net-_u13-pad1_ net-_u24-pad6_ u24
a24 net-_u24-pad6_ net-_u29-pad2_ net-_u1-pad15_ u32
a25 net-_u1-pad5_ net-_u21-pad4_ u5
* Schematic Name:                             d_nand, NgSpice Name: d_nand
.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
* Schematic Name:                             d_and, NgSpice Name: d_and
.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
* Schematic Name:                             d_and, NgSpice Name: d_and
.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
* Schematic Name:                             d_or, NgSpice Name: d_or
.model u17 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
* Schematic Name:                             d_dff, NgSpice Name: d_dff
.model u21 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
* Schematic Name:                             d_tristate, NgSpice Name: d_tristate
.model u29 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) 
* Schematic Name:                             d_and, NgSpice Name: d_and
.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
* Schematic Name:                             d_and, NgSpice Name: d_and
.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
* Schematic Name:                             d_or, NgSpice Name: d_or
.model u18 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
* Schematic Name:                             d_dff, NgSpice Name: d_dff
.model u22 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
* Schematic Name:                             d_tristate, NgSpice Name: d_tristate
.model u30 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) 
* Schematic Name:                             d_nand, NgSpice Name: d_nand
.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
* Schematic Name:                             d_and, NgSpice Name: d_and
.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
* Schematic Name:                             d_and, NgSpice Name: d_and
.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
* Schematic Name:                             d_or, NgSpice Name: d_or
.model u19 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
* Schematic Name:                             d_dff, NgSpice Name: d_dff
.model u23 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
* Schematic Name:                             d_tristate, NgSpice Name: d_tristate
.model u31 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) 
* Schematic Name:                             d_and, NgSpice Name: d_and
.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
* Schematic Name:                             d_and, NgSpice Name: d_and
.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
* Schematic Name:                             d_or, NgSpice Name: d_or
.model u20 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
* Schematic Name:                             d_dff, NgSpice Name: d_dff
.model u24 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
* Schematic Name:                             d_tristate, NgSpice Name: d_tristate
.model u32 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) 
* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
.tran 0e-00 0e-00 0e-00

* Control Statements 
.control
run
print allv > plot_data_v.txt
print alli > plot_data_i.txt
.endc
.end