* c:\fossee\esim\library\subcircuitlibrary\7447\7447.cir .include 4_and.sub .include 3_and.sub * u3 net-_u1-pad1_ net-_u1-pad6_ net-_u10-pad1_ d_nand * u4 net-_u1-pad2_ net-_u1-pad6_ net-_u11-pad1_ d_nand * u5 net-_u1-pad3_ net-_u1-pad6_ net-_u12-pad1_ d_nand * u2 net-_u1-pad4_ net-_u13-pad1_ d_inverter * u6 net-_u1-pad7_ net-_u6-pad2_ d_inverter x1 net-_u1-pad6_ net-_u6-pad2_ net-_u11-pad1_ net-_u12-pad1_ net-_u33-pad1_ 4_and * u9 net-_u13-pad1_ net-_u10-pad1_ net-_u33-pad2_ d_and * u10 net-_u10-pad1_ net-_u1-pad5_ net-_u10-pad3_ d_nand * u11 net-_u11-pad1_ net-_u1-pad5_ net-_u11-pad3_ d_nand * u12 net-_u12-pad1_ net-_u1-pad5_ net-_u12-pad3_ d_nand * u13 net-_u13-pad1_ net-_u1-pad5_ net-_u13-pad3_ d_nand * u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port * u14 net-_u11-pad3_ net-_u13-pad3_ net-_u14-pad3_ d_and * u15 net-_u10-pad1_ net-_u12-pad3_ net-_u15-pad3_ d_and x10 net-_u10-pad3_ net-_u11-pad1_ net-_u12-pad1_ net-_u13-pad1_ ? 4_and * u16 net-_u11-pad3_ net-_u13-pad3_ net-_u16-pad3_ d_and x2 net-_u10-pad3_ net-_u11-pad1_ net-_u12-pad3_ net-_u23-pad2_ 3_and x3 net-_u10-pad1_ net-_u11-pad3_ net-_u12-pad3_ net-_u36-pad2_ 3_and * u17 net-_u12-pad3_ net-_u13-pad3_ net-_u17-pad3_ d_and x4 net-_u10-pad1_ net-_u11-pad3_ net-_u12-pad1_ net-_u27-pad2_ 3_and x5 net-_u10-pad3_ net-_u11-pad1_ net-_u12-pad1_ net-_u24-pad1_ 3_and x6 net-_u10-pad1_ net-_u11-pad1_ net-_u12-pad3_ net-_u24-pad2_ 3_and x7 net-_u10-pad3_ net-_u11-pad3_ net-_u12-pad3_ net-_u37-pad2_ 3_and * u21 net-_u10-pad3_ net-_u21-pad2_ d_buffer * u18 net-_u11-pad1_ net-_u12-pad3_ net-_u18-pad3_ d_and * u19 net-_u10-pad3_ net-_u11-pad3_ net-_u19-pad3_ d_and * u20 net-_u11-pad3_ net-_u12-pad1_ net-_u20-pad3_ d_and x8 net-_u10-pad3_ net-_u12-pad1_ net-_u13-pad1_ net-_u38-pad2_ 3_and x9 net-_u10-pad3_ net-_u11-pad3_ net-_u12-pad3_ net-_u28-pad1_ 3_and x11 net-_u11-pad1_ net-_u12-pad1_ net-_u13-pad1_ net-_u1-pad6_ net-_u28-pad2_ 4_and * u27 net-_u17-pad3_ net-_u27-pad2_ net-_u27-pad3_ d_nor * u26 net-_u21-pad2_ net-_u18-pad3_ net-_u26-pad3_ d_nor * u28 net-_u28-pad1_ net-_u28-pad2_ net-_u28-pad3_ d_nor * u22 net-_u14-pad3_ net-_u15-pad3_ net-_u22-pad3_ d_nor * u29 net-_u22-pad3_ net-_u22-pad3_ net-_u29-pad3_ d_nor * u35 net-_u29-pad3_ ? net-_u35-pad3_ d_nor * u23 net-_u16-pad3_ net-_u23-pad2_ net-_u23-pad3_ d_nor * u30 net-_u23-pad3_ net-_u23-pad3_ net-_u30-pad3_ d_nor * u36 net-_u30-pad3_ net-_u36-pad2_ net-_u36-pad3_ d_nor * u24 net-_u24-pad1_ net-_u24-pad2_ net-_u24-pad3_ d_nor * u31 net-_u24-pad3_ net-_u24-pad3_ net-_u31-pad3_ d_nor * u37 net-_u31-pad3_ net-_u37-pad2_ net-_u37-pad3_ d_nor * u25 net-_u19-pad3_ net-_u20-pad3_ net-_u25-pad3_ d_nor * u32 net-_u25-pad3_ net-_u25-pad3_ net-_u32-pad3_ d_nor * u38 net-_u32-pad3_ net-_u38-pad2_ net-_u38-pad3_ d_nor * u33 net-_u33-pad1_ net-_u33-pad2_ net-_u1-pad5_ d_nand * u39 net-_u35-pad3_ net-_u1-pad8_ d_inverter * u40 net-_u36-pad3_ net-_u1-pad9_ d_inverter * u34 net-_u27-pad3_ net-_u1-pad10_ d_inverter * u41 net-_u37-pad3_ net-_u1-pad11_ d_inverter * u8 net-_u26-pad3_ net-_u1-pad12_ d_inverter * u42 net-_u38-pad3_ net-_u1-pad13_ d_inverter * u7 net-_u28-pad3_ net-_u1-pad14_ d_inverter a1 [net-_u1-pad1_ net-_u1-pad6_ ] net-_u10-pad1_ u3 a2 [net-_u1-pad2_ net-_u1-pad6_ ] net-_u11-pad1_ u4 a3 [net-_u1-pad3_ net-_u1-pad6_ ] net-_u12-pad1_ u5 a4 net-_u1-pad4_ net-_u13-pad1_ u2 a5 net-_u1-pad7_ net-_u6-pad2_ u6 a6 [net-_u13-pad1_ net-_u10-pad1_ ] net-_u33-pad2_ u9 a7 [net-_u10-pad1_ net-_u1-pad5_ ] net-_u10-pad3_ u10 a8 [net-_u11-pad1_ net-_u1-pad5_ ] net-_u11-pad3_ u11 a9 [net-_u12-pad1_ net-_u1-pad5_ ] net-_u12-pad3_ u12 a10 [net-_u13-pad1_ net-_u1-pad5_ ] net-_u13-pad3_ u13 a11 [net-_u11-pad3_ net-_u13-pad3_ ] net-_u14-pad3_ u14 a12 [net-_u10-pad1_ net-_u12-pad3_ ] net-_u15-pad3_ u15 a13 [net-_u11-pad3_ net-_u13-pad3_ ] net-_u16-pad3_ u16 a14 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u17-pad3_ u17 a15 net-_u10-pad3_ net-_u21-pad2_ u21 a16 [net-_u11-pad1_ net-_u12-pad3_ ] net-_u18-pad3_ u18 a17 [net-_u10-pad3_ net-_u11-pad3_ ] net-_u19-pad3_ u19 a18 [net-_u11-pad3_ net-_u12-pad1_ ] net-_u20-pad3_ u20 a19 [net-_u17-pad3_ net-_u27-pad2_ ] net-_u27-pad3_ u27 a20 [net-_u21-pad2_ net-_u18-pad3_ ] net-_u26-pad3_ u26 a21 [net-_u28-pad1_ net-_u28-pad2_ ] net-_u28-pad3_ u28 a22 [net-_u14-pad3_ net-_u15-pad3_ ] net-_u22-pad3_ u22 a23 [net-_u22-pad3_ net-_u22-pad3_ ] net-_u29-pad3_ u29 a24 [net-_u29-pad3_ ? ] net-_u35-pad3_ u35 a25 [net-_u16-pad3_ net-_u23-pad2_ ] net-_u23-pad3_ u23 a26 [net-_u23-pad3_ net-_u23-pad3_ ] net-_u30-pad3_ u30 a27 [net-_u30-pad3_ net-_u36-pad2_ ] net-_u36-pad3_ u36 a28 [net-_u24-pad1_ net-_u24-pad2_ ] net-_u24-pad3_ u24 a29 [net-_u24-pad3_ net-_u24-pad3_ ] net-_u31-pad3_ u31 a30 [net-_u31-pad3_ net-_u37-pad2_ ] net-_u37-pad3_ u37 a31 [net-_u19-pad3_ net-_u20-pad3_ ] net-_u25-pad3_ u25 a32 [net-_u25-pad3_ net-_u25-pad3_ ] net-_u32-pad3_ u32 a33 [net-_u32-pad3_ net-_u38-pad2_ ] net-_u38-pad3_ u38 a34 [net-_u33-pad1_ net-_u33-pad2_ ] net-_u1-pad5_ u33 a35 net-_u35-pad3_ net-_u1-pad8_ u39 a36 net-_u36-pad3_ net-_u1-pad9_ u40 a37 net-_u27-pad3_ net-_u1-pad10_ u34 a38 net-_u37-pad3_ net-_u1-pad11_ u41 a39 net-_u26-pad3_ net-_u1-pad12_ u8 a40 net-_u38-pad3_ net-_u1-pad13_ u42 a41 net-_u28-pad3_ net-_u1-pad14_ u7 * Schematic Name: d_nand, NgSpice Name: d_nand .model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_nand, NgSpice Name: d_nand .model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_nand, NgSpice Name: d_nand .model u5 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_and, NgSpice Name: d_and .model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_nand, NgSpice Name: d_nand .model u10 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_nand, NgSpice Name: d_nand .model u11 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_nand, NgSpice Name: d_nand .model u12 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_nand, NgSpice Name: d_nand .model u13 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_and, NgSpice Name: d_and .model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_and, NgSpice Name: d_and .model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_and, NgSpice Name: d_and .model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_and, NgSpice Name: d_and .model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_buffer, NgSpice Name: d_buffer .model u21 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_and, NgSpice Name: d_and .model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_and, NgSpice Name: d_and .model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_and, NgSpice Name: d_and .model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_nor, NgSpice Name: d_nor .model u27 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_nor, NgSpice Name: d_nor .model u26 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_nor, NgSpice Name: d_nor .model u28 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_nor, NgSpice Name: d_nor .model u22 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_nor, NgSpice Name: d_nor .model u29 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_nor, NgSpice Name: d_nor .model u35 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_nor, NgSpice Name: d_nor .model u23 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_nor, NgSpice Name: d_nor .model u30 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_nor, NgSpice Name: d_nor .model u36 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_nor, NgSpice Name: d_nor .model u24 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_nor, NgSpice Name: d_nor .model u31 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_nor, NgSpice Name: d_nor .model u37 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_nor, NgSpice Name: d_nor .model u25 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_nor, NgSpice Name: d_nor .model u32 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_nor, NgSpice Name: d_nor .model u38 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_nand, NgSpice Name: d_nand .model u33 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u39 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u40 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u41 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u42 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) .tran 0e-00 0e-00 0e-00 * Control Statements .control run print allv > plot_data_v.txt print alli > plot_data_i.txt .endc .end