* Subcircuit CD4532B .subckt CD4532B net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? * c:\fossee_mains\fossee\esim\library\subcircuitlibrary\cd4532b\cd4532b.cir .include 4_and.sub .include 4_OR.sub * u2 net-_u1-pad11_ net-_u2-pad2_ d_inverter * u3 net-_u1-pad12_ net-_u10-pad1_ d_inverter * u4 net-_u1-pad13_ net-_u4-pad2_ d_inverter * u5 net-_u1-pad1_ net-_u11-pad1_ d_inverter * u7 net-_u1-pad2_ net-_u12-pad1_ d_inverter * u8 net-_u1-pad3_ net-_u13-pad1_ d_inverter * u6 net-_u1-pad4_ net-_u6-pad2_ d_inverter * u9 net-_u1-pad5_ net-_u14-pad1_ d_inverter * u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter * u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter * u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter * u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter * u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter x1 net-_u2-pad2_ net-_u10-pad2_ net-_u11-pad2_ net-_u13-pad2_ net-_x1-pad5_ 4_OR x2 net-_u13-pad2_ net-_u11-pad2_ net-_u4-pad2_ ? net-_x2-pad5_ 4_OR x3 net-_u10-pad1_ net-_u11-pad2_ net-_u12-pad2_ ? net-_x3-pad5_ 4_OR x4 net-_u4-pad2_ net-_u11-pad2_ net-_u12-pad2_ ? net-_x4-pad5_ 4_OR * u22 net-_u22-pad1_ net-_u16-pad1_ d_inverter * u23 net-_u23-pad1_ net-_u15-pad1_ d_inverter * u24 net-_u16-pad1_ net-_u15-pad1_ net-_u24-pad3_ d_nand x5 net-_x1-pad5_ net-_x2-pad5_ net-_u19-pad3_ net-_u6-pad2_ net-_u25-pad1_ 4_and x6 net-_x3-pad5_ net-_x4-pad5_ net-_u13-pad1_ net-_u6-pad2_ net-_u27-pad1_ 4_and x7 net-_u11-pad1_ net-_u12-pad1_ net-_u13-pad1_ net-_u6-pad2_ net-_u26-pad1_ 4_and * u25 net-_u25-pad1_ net-_u25-pad2_ d_inverter * u27 net-_u27-pad1_ net-_u27-pad2_ d_inverter * u26 net-_u26-pad1_ net-_u26-pad2_ d_inverter * u29 net-_u25-pad2_ net-_u14-pad2_ net-_u29-pad3_ d_nand * u30 net-_u27-pad2_ net-_u14-pad2_ net-_u30-pad3_ d_nand * u31 net-_u26-pad2_ net-_u14-pad2_ net-_u31-pad3_ d_nand * u32 net-_u24-pad3_ net-_u1-pad5_ net-_u32-pad3_ d_nand * u34 net-_u29-pad3_ net-_u1-pad9_ d_inverter * u33 net-_u30-pad3_ net-_u1-pad7_ d_inverter * u36 net-_u31-pad3_ net-_u1-pad6_ d_inverter * u37 net-_u32-pad3_ net-_u1-pad14_ d_inverter * u35 net-_u20-pad3_ net-_u1-pad15_ d_inverter * u19 net-_u13-pad2_ net-_u12-pad1_ net-_u19-pad3_ d_or x8 net-_u1-pad4_ net-_u1-pad3_ net-_u1-pad2_ net-_u1-pad1_ net-_u22-pad1_ 4_OR x9 net-_u1-pad13_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad10_ net-_u23-pad1_ 4_OR * u16 net-_u16-pad1_ net-_u16-pad2_ d_inverter * u17 net-_u1-pad5_ net-_u17-pad2_ d_inverter * u15 net-_u15-pad1_ net-_u15-pad2_ d_inverter * u18 net-_u15-pad2_ net-_u16-pad2_ net-_u18-pad3_ d_or * u20 net-_u18-pad3_ net-_u17-pad2_ net-_u20-pad3_ d_or a1 net-_u1-pad11_ net-_u2-pad2_ u2 a2 net-_u1-pad12_ net-_u10-pad1_ u3 a3 net-_u1-pad13_ net-_u4-pad2_ u4 a4 net-_u1-pad1_ net-_u11-pad1_ u5 a5 net-_u1-pad2_ net-_u12-pad1_ u7 a6 net-_u1-pad3_ net-_u13-pad1_ u8 a7 net-_u1-pad4_ net-_u6-pad2_ u6 a8 net-_u1-pad5_ net-_u14-pad1_ u9 a9 net-_u10-pad1_ net-_u10-pad2_ u10 a10 net-_u11-pad1_ net-_u11-pad2_ u11 a11 net-_u12-pad1_ net-_u12-pad2_ u12 a12 net-_u13-pad1_ net-_u13-pad2_ u13 a13 net-_u14-pad1_ net-_u14-pad2_ u14 a14 net-_u22-pad1_ net-_u16-pad1_ u22 a15 net-_u23-pad1_ net-_u15-pad1_ u23 a16 [net-_u16-pad1_ net-_u15-pad1_ ] net-_u24-pad3_ u24 a17 net-_u25-pad1_ net-_u25-pad2_ u25 a18 net-_u27-pad1_ net-_u27-pad2_ u27 a19 net-_u26-pad1_ net-_u26-pad2_ u26 a20 [net-_u25-pad2_ net-_u14-pad2_ ] net-_u29-pad3_ u29 a21 [net-_u27-pad2_ net-_u14-pad2_ ] net-_u30-pad3_ u30 a22 [net-_u26-pad2_ net-_u14-pad2_ ] net-_u31-pad3_ u31 a23 [net-_u24-pad3_ net-_u1-pad5_ ] net-_u32-pad3_ u32 a24 net-_u29-pad3_ net-_u1-pad9_ u34 a25 net-_u30-pad3_ net-_u1-pad7_ u33 a26 net-_u31-pad3_ net-_u1-pad6_ u36 a27 net-_u32-pad3_ net-_u1-pad14_ u37 a28 net-_u20-pad3_ net-_u1-pad15_ u35 a29 [net-_u13-pad2_ net-_u12-pad1_ ] net-_u19-pad3_ u19 a30 net-_u16-pad1_ net-_u16-pad2_ u16 a31 net-_u1-pad5_ net-_u17-pad2_ u17 a32 net-_u15-pad1_ net-_u15-pad2_ u15 a33 [net-_u15-pad2_ net-_u16-pad2_ ] net-_u18-pad3_ u18 a34 [net-_u18-pad3_ net-_u17-pad2_ ] net-_u20-pad3_ u20 * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u2 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u3 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u4 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u5 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u7 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u8 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u6 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u9 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u10 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u11 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u12 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u13 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u14 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u22 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u23 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) * Schematic Name: d_nand, NgSpice Name: d_nand .model u24 d_nand(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u25 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u27 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u26 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) * Schematic Name: d_nand, NgSpice Name: d_nand .model u29 d_nand(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) * Schematic Name: d_nand, NgSpice Name: d_nand .model u30 d_nand(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) * Schematic Name: d_nand, NgSpice Name: d_nand .model u31 d_nand(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) * Schematic Name: d_nand, NgSpice Name: d_nand .model u32 d_nand(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u34 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u33 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u36 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u37 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u35 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) * Schematic Name: d_or, NgSpice Name: d_or .model u19 d_or(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u16 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u17 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u15 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) * Schematic Name: d_or, NgSpice Name: d_or .model u18 d_or(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) * Schematic Name: d_or, NgSpice Name: d_or .model u20 d_or(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) * Control Statements .ends CD4532B