* Subcircuit CD4066B .subckt CD4066B net-_u1-pad1_ net-_m1-pad1_ net-_m2-pad3_ net-_m4-pad1_ gnd * c:\fossee\esim\library\subcircuitlibrary\cd4066b\cd4066b.cir .include NMOS-0.5um.lib .include PMOS-0.5um.lib * u3 net-_u2-pad2_ net-_u3-pad2_ d_inverter * u4 net-_u3-pad2_ net-_u4-pad2_ d_inverter * u7 net-_u4-pad2_ net-_u6-pad1_ d_inverter m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ ? mos_p W=100u L=5u M=1 m3 net-_m1-pad1_ net-_m3-pad2_ net-_m1-pad3_ ? mos_n W=100u L=5u M=1 m2 net-_m1-pad3_ net-_m1-pad2_ net-_m2-pad3_ net-_m2-pad3_ mos_n W=100u L=5u M=1 m4 net-_m4-pad1_ net-_m1-pad2_ net-_m1-pad1_ ? mos_p W=100u L=5u M=1 m5 net-_m4-pad1_ net-_m3-pad2_ net-_m1-pad1_ net-_m1-pad3_ mos_n W=100u L=5u M=1 * u2 net-_u1-pad1_ net-_u2-pad2_ adc_bridge_1 * u6 net-_u6-pad1_ net-_m1-pad2_ dac_bridge_1 * u5 net-_u4-pad2_ net-_m3-pad2_ dac_bridge_1 a1 net-_u2-pad2_ net-_u3-pad2_ u3 a2 net-_u3-pad2_ net-_u4-pad2_ u4 a3 net-_u4-pad2_ net-_u6-pad1_ u7 a4 [net-_u1-pad1_ ] [net-_u2-pad2_ ] u2 a5 [net-_u6-pad1_ ] [net-_m1-pad2_ ] u6 a6 [net-_u4-pad2_ ] [net-_m3-pad2_ ] u5 * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge .model u2 adc_bridge(in_low=0 in_high=5 rise_delay=1.0e-9 fall_delay=1.0e-9 ) * Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge .model u6 dac_bridge(out_low= 0 out_high= 5 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) * Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge .model u5 dac_bridge(out_low= 0 out_high= 5 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) * Control Statements .ends CD4066B