* c:\fossee\esim\library\subcircuitlibrary\cd4035bm\cd4035bm.cir .include NMOS-180nm.lib .include PMOS-180nm.lib * u3 net-_u1-pad3_ net-_u15-pad1_ d_inverter m3 net-_m1-pad3_ net-_m10-pad2_ net-_m1-pad1_ vdd CMOSP W=100u L=100u M=1 m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ vss CMOSN W=100u L=100u M=1 * u9 net-_u15-pad1_ net-_m10-pad2_ dac_bridge_1 * u15 net-_u15-pad1_ net-_u14-pad1_ d_inverter * u14 net-_u14-pad1_ net-_m1-pad2_ dac_bridge_1 m4 net-_m1-pad3_ net-_m1-pad2_ net-_m2-pad1_ vdd CMOSP W=100u L=100u M=1 m2 net-_m2-pad1_ net-_m10-pad2_ net-_m1-pad3_ vss CMOSN W=100u L=100u M=1 * u4 net-_u16-pad5_ net-_u1-pad4_ net-_u10-pad1_ d_nand * u5 net-_u16-pad5_ net-_u2-pad2_ net-_u10-pad2_ d_and * u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_nor * u2 net-_u1-pad5_ net-_u2-pad2_ d_inverter * u16 net-_u13-pad2_ net-_u16-pad2_ net-_u1-pad17_ net-_u12-pad2_ net-_u16-pad5_ net-_u16-pad6_ d_dff m7 net-_m5-pad3_ net-_m10-pad2_ net-_m5-pad1_ vdd CMOSP W=100u L=100u M=1 m5 net-_m5-pad1_ net-_m5-pad2_ net-_m5-pad3_ vss CMOSN W=100u L=100u M=1 * u22 net-_u15-pad1_ net-_u21-pad1_ d_inverter * u21 net-_u21-pad1_ net-_m5-pad2_ dac_bridge_1 m8 net-_m5-pad3_ net-_m5-pad2_ net-_m6-pad1_ vdd CMOSP W=100u L=100u M=1 m6 net-_m6-pad1_ net-_m10-pad2_ net-_m5-pad3_ vss CMOSN W=100u L=100u M=1 * u23 net-_u20-pad2_ net-_u16-pad2_ net-_u1-pad17_ net-_u12-pad2_ ? net-_u23-pad6_ d_dff * u24 net-_u23-pad6_ net-_u24-pad2_ d_buffer * u17 net-_u16-pad6_ net-_u17-pad2_ d_buffer m11 net-_m10-pad3_ net-_m10-pad2_ net-_m11-pad3_ vdd CMOSP W=100u L=100u M=1 m9 net-_m11-pad3_ net-_m12-pad2_ net-_m10-pad3_ vss CMOSN W=100u L=100u M=1 * u29 net-_u15-pad1_ net-_u28-pad1_ d_inverter * u28 net-_u28-pad1_ net-_m12-pad2_ dac_bridge_1 m12 net-_m10-pad3_ net-_m12-pad2_ net-_m10-pad1_ vdd CMOSP W=100u L=100u M=1 m10 net-_m10-pad1_ net-_m10-pad2_ net-_m10-pad3_ vss CMOSN W=100u L=100u M=1 * u30 net-_u27-pad2_ net-_u16-pad2_ net-_u1-pad17_ net-_u12-pad2_ ? net-_u30-pad6_ d_dff * u31 net-_u30-pad6_ net-_u31-pad2_ d_buffer m15 net-_m13-pad3_ net-_m10-pad2_ net-_m13-pad1_ vdd CMOSP W=100u L=100u M=1 m13 net-_m13-pad1_ net-_m13-pad2_ net-_m13-pad3_ vss CMOSN W=100u L=100u M=1 * u36 net-_u15-pad1_ net-_u35-pad1_ d_inverter * u35 net-_u35-pad1_ net-_m13-pad2_ dac_bridge_1 m16 net-_m13-pad3_ net-_m13-pad2_ net-_m14-pad1_ vdd CMOSP W=100u L=100u M=1 m14 net-_m14-pad1_ net-_m10-pad2_ net-_m13-pad3_ vss CMOSN W=100u L=100u M=1 * u37 net-_u34-pad2_ net-_u16-pad2_ net-_u1-pad17_ net-_u12-pad2_ ? net-_u37-pad6_ d_dff * u38 net-_u37-pad6_ net-_u38-pad2_ d_buffer * u6 net-_u1-pad6_ net-_u16-pad2_ d_inverter * u7 net-_u1-pad7_ net-_u12-pad1_ d_inverter * u12 net-_u12-pad1_ net-_u12-pad2_ d_buffer * u8 net-_u1-pad8_ net-_u18-pad2_ d_inverter * u1 vdd vss net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_m1-pad1_ net-_m5-pad1_ net-_m11-pad3_ net-_m13-pad1_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ port * u18 net-_u17-pad2_ net-_u18-pad2_ net-_u1-pad13_ d_xor * u25 net-_u24-pad2_ net-_u18-pad2_ net-_u1-pad14_ d_xor * u32 net-_u31-pad2_ net-_u18-pad2_ net-_u1-pad15_ d_xor * u39 net-_u38-pad2_ net-_u18-pad2_ net-_u1-pad16_ d_xor * u34 net-_m13-pad3_ net-_u34-pad2_ adc_bridge_1 * u27 net-_m10-pad3_ net-_u27-pad2_ adc_bridge_1 * u20 net-_m5-pad3_ net-_u20-pad2_ adc_bridge_1 * u13 net-_m1-pad3_ net-_u13-pad2_ adc_bridge_1 * u19 net-_u17-pad2_ net-_m6-pad1_ dac_bridge_1 * u26 net-_u24-pad2_ net-_m10-pad1_ dac_bridge_1 * u33 net-_u31-pad2_ net-_m14-pad1_ dac_bridge_1 * u11 net-_u10-pad3_ net-_m2-pad1_ dac_bridge_1 a1 net-_u1-pad3_ net-_u15-pad1_ u3 a2 [net-_u15-pad1_ ] [net-_m10-pad2_ ] u9 a3 net-_u15-pad1_ net-_u14-pad1_ u15 a4 [net-_u14-pad1_ ] [net-_m1-pad2_ ] u14 a5 [net-_u16-pad5_ net-_u1-pad4_ ] net-_u10-pad1_ u4 a6 [net-_u16-pad5_ net-_u2-pad2_ ] net-_u10-pad2_ u5 a7 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 a8 net-_u1-pad5_ net-_u2-pad2_ u2 a9 net-_u13-pad2_ net-_u16-pad2_ net-_u1-pad17_ net-_u12-pad2_ net-_u16-pad5_ net-_u16-pad6_ u16 a10 net-_u15-pad1_ net-_u21-pad1_ u22 a11 [net-_u21-pad1_ ] [net-_m5-pad2_ ] u21 a12 net-_u20-pad2_ net-_u16-pad2_ net-_u1-pad17_ net-_u12-pad2_ ? net-_u23-pad6_ u23 a13 net-_u23-pad6_ net-_u24-pad2_ u24 a14 net-_u16-pad6_ net-_u17-pad2_ u17 a15 net-_u15-pad1_ net-_u28-pad1_ u29 a16 [net-_u28-pad1_ ] [net-_m12-pad2_ ] u28 a17 net-_u27-pad2_ net-_u16-pad2_ net-_u1-pad17_ net-_u12-pad2_ ? net-_u30-pad6_ u30 a18 net-_u30-pad6_ net-_u31-pad2_ u31 a19 net-_u15-pad1_ net-_u35-pad1_ u36 a20 [net-_u35-pad1_ ] [net-_m13-pad2_ ] u35 a21 net-_u34-pad2_ net-_u16-pad2_ net-_u1-pad17_ net-_u12-pad2_ ? net-_u37-pad6_ u37 a22 net-_u37-pad6_ net-_u38-pad2_ u38 a23 net-_u1-pad6_ net-_u16-pad2_ u6 a24 net-_u1-pad7_ net-_u12-pad1_ u7 a25 net-_u12-pad1_ net-_u12-pad2_ u12 a26 net-_u1-pad8_ net-_u18-pad2_ u8 a27 [net-_u17-pad2_ net-_u18-pad2_ ] net-_u1-pad13_ u18 a28 [net-_u24-pad2_ net-_u18-pad2_ ] net-_u1-pad14_ u25 a29 [net-_u31-pad2_ net-_u18-pad2_ ] net-_u1-pad15_ u32 a30 [net-_u38-pad2_ net-_u18-pad2_ ] net-_u1-pad16_ u39 a31 [net-_m13-pad3_ ] [net-_u34-pad2_ ] u34 a32 [net-_m10-pad3_ ] [net-_u27-pad2_ ] u27 a33 [net-_m5-pad3_ ] [net-_u20-pad2_ ] u20 a34 [net-_m1-pad3_ ] [net-_u13-pad2_ ] u13 a35 [net-_u17-pad2_ ] [net-_m6-pad1_ ] u19 a36 [net-_u24-pad2_ ] [net-_m10-pad1_ ] u26 a37 [net-_u31-pad2_ ] [net-_m14-pad1_ ] u33 a38 [net-_u10-pad3_ ] [net-_m2-pad1_ ] u11 * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge .model u9 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge .model u14 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) * Schematic Name: d_nand, NgSpice Name: d_nand .model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_and, NgSpice Name: d_and .model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_nor, NgSpice Name: d_nor .model u10 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_dff, NgSpice Name: d_dff .model u16 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge .model u21 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) * Schematic Name: d_dff, NgSpice Name: d_dff .model u23 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) * Schematic Name: d_buffer, NgSpice Name: d_buffer .model u24 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_buffer, NgSpice Name: d_buffer .model u17 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge .model u28 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) * Schematic Name: d_dff, NgSpice Name: d_dff .model u30 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) * Schematic Name: d_buffer, NgSpice Name: d_buffer .model u31 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u36 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge .model u35 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) * Schematic Name: d_dff, NgSpice Name: d_dff .model u37 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) * Schematic Name: d_buffer, NgSpice Name: d_buffer .model u38 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_buffer, NgSpice Name: d_buffer .model u12 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_xor, NgSpice Name: d_xor .model u18 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_xor, NgSpice Name: d_xor .model u25 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_xor, NgSpice Name: d_xor .model u32 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: d_xor, NgSpice Name: d_xor .model u39 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) * Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge .model u34 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) * Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge .model u27 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) * Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge .model u20 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) * Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge .model u13 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) * Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge .model u19 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) * Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge .model u26 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) * Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge .model u33 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) * Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge .model u11 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) .tran 0e-00 0e-00 0e-00 * Control Statements .control run print allv > plot_data_v.txt print alli > plot_data_i.txt .endc .end