* c:\fossee\esim\library\subcircuitlibrary\3_nor\3_nor.cir

.include NMOS-180nm.lib
.include PMOS-180nm.lib
m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1
m5 net-_m1-pad1_ net-_m3-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1
m6 net-_m1-pad1_ net-_m4-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1
m2 net-_m2-pad1_ net-_m1-pad2_ net-_m2-pad3_ net-_m2-pad1_ CMOSP W=100u L=100u M=1
m3 net-_m2-pad3_ net-_m3-pad2_ net-_m3-pad3_ net-_m2-pad1_ CMOSP W=100u L=100u M=1
m4 net-_m3-pad3_ net-_m4-pad2_ net-_m1-pad1_ net-_m2-pad1_ CMOSP W=100u L=100u M=1
* u4  net-_u3-pad2_ net-_u1-pad6_ d_buffer
* u3  net-_m1-pad1_ net-_u3-pad2_ adc_bridge_1
* u2  net-_u1-pad3_ net-_u1-pad1_ net-_u1-pad2_ net-_m1-pad2_ net-_m3-pad2_ net-_m4-pad2_ dac_bridge_3
* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_m2-pad1_ net-_m1-pad3_ net-_u1-pad6_ port
a1 net-_u3-pad2_ net-_u1-pad6_ u4
a2 [net-_m1-pad1_ ] [net-_u3-pad2_ ] u3
a3 [net-_u1-pad3_ net-_u1-pad1_ net-_u1-pad2_ ] [net-_m1-pad2_ net-_m3-pad2_ net-_m4-pad2_ ] u2
* Schematic Name:                             d_buffer, NgSpice Name: d_buffer
.model u4 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
.model u3 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
* Schematic Name:                             dac_bridge_3, NgSpice Name: dac_bridge
.model u2 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
.tran 0e-00 0e-00 0e-00

* Control Statements 
.control
run
print allv > plot_data_v.txt
print alli > plot_data_i.txt
.endc
.end